This repository contains public pre-releases of features for AMD or features being worked on by AMD. Most users should use the main gem5 repo for their work (public/gem5).

Clone this repo:
  1. 5320a97 sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy(). by Xiaoyu Ma · 8 weeks ago master
  2. cc51037 util/m5: add Android.mk by Earl Ou · 4 months ago
  3. b622601 arch-riscv: Don't crash when printing unknown CSRs by Alec Roelke · 6 weeks ago
  4. 1437a24 mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocol by Nikos Nikoleris · 3 weeks ago
  5. 9737d93 mem-ruby: Remove function that maps responses to a DMA engine by Nikos Nikoleris · 3 weeks ago
  6. c6c2227 mem-ruby: Add support for multiple DMA engines in MESI_Two_Level by Nikos Nikoleris · 3 weeks ago
  7. f3d4d6f cpu: Make the CPU's TLB parameter a BaseTLB. by Gabe Black · 2 weeks ago
  8. f96e542 arm, power: Make the python TLB simobjects inherit from BaseTLB. by Gabe Black · 2 weeks ago
  9. ad0056d arch,mem: Remove the default value for page size. by Gabe Black · 4 weeks ago
  10. 54a9d47 arch,mem: Move page table construction into the arch classes. by Gabe Black · 4 weeks ago
  11. c2f3f6d configs: Fill in the cpu.isa field in etrace_replay.py since no default are provided now by Chen Zou · 3 weeks ago
  12. 1246617 style: change C/C++ source permissions to noexec by BKP · 14 days ago
  13. e228943 arch-riscv: Make use of ImmOp's polymorphism by Alec Roelke · 7 weeks ago
  14. 78524bd alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. by Gabe Black · 5 weeks ago
  15. 3fb4d59 arch-riscv,sim: Support clone syscall in RISC-V by Tuan Ta · 4 months ago
  16. e823650 mem-cache: Prune unnecessary writebacks in exclusive caches by Nikos Nikoleris · 5 months ago
  17. 50f9ef0 util: Add the missing wakecpu m5op in X86. by Hanhwi Jang · 7 weeks ago
  18. f4ac367 util: resolve m5op name mismatching in m5op headers. by Hanhwi Jang · 7 weeks ago
  19. 3cc77c9 cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults. by Gabe Black · 2 weeks ago
  20. ed8b7f2 cpu: Add a NotAnInst flag to the BaseDynInst class. by Gabe Black · 2 weeks ago