src/cpu/reg_class_impl.hh

/*
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 * this software without specific prior written permission.
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 * Authors: Rekai Gonzalez
 */

#ifndef __CPU__REG_CLASS_IMPL_HH__
#define __CPU__REG_CLASS_IMPL_HH__

#include <cassert>
#include <cstddef>
#include <iostream>

#include "arch/registers.hh"
#include "config/the_isa.hh"
#include "cpu/reg_class.hh"

bool RegId::isZeroReg() const
{
    return ((regClass == IntRegClass && regIdx == TheISA::ZeroReg) ||
            (THE_ISA == ALPHA_ISA && regClass == FloatRegClass &&
             regIdx == TheISA::ZeroReg));
}

static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;

RegIndex RegId::flatIndex() const {
    switch (regClass) {
    case IntRegClass:
    case FloatRegClass:
    case VecRegClass:
    case CCRegClass:
    case MiscRegClass:
        return regIdx;
    case VecElemClass:
        return Scale*regIdx + elemIdx;
    }
    panic("Trying to flatten a register without class!");
    return -1;
}

#endif // __CPU__REG_CLASS_IMPL_HH__