# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# Authors: Brad Beckmann

from m5.SimObject import SimObject
from MemObject import MemObject
from m5.params import *
from m5.proxy import *

class DirectedGenerator(SimObject):
    type = 'DirectedGenerator'
    abstract = True
    cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh"
    num_cpus = Param.Int("num of cpus")
    system = Param.System(Parent.any, "System we belong to")

class SeriesRequestGenerator(DirectedGenerator):
    type = 'SeriesRequestGenerator'
    cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh"
    addr_increment_size = Param.Int(64, "address increment size")
    num_series = Param.UInt32(1,
        "number of different address streams to generate")
    percent_writes = Param.Percent(50, "percent of access that are writes")

class InvalidateGenerator(DirectedGenerator):
    type = 'InvalidateGenerator'
    cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh"
    addr_increment_size = Param.Int(64, "address increment size")

class RubyDirectedTester(MemObject):
    type = 'RubyDirectedTester'
    cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh"
    cpuPort = VectorMasterPort("the cpu ports")
    requests_to_complete = Param.Int("checks to complete")
    generator = Param.DirectedGenerator("the request generator")