)]}'
{
  "commit": "5320a97ced43d4452014ff54c0ba45246db90a00",
  "tree": "8048a3c9f79b83deb64b7c5454bd560b2b115208",
  "parents": [
    "cc51037e8074949bc9e7638babfb597490d007ec"
  ],
  "author": {
    "name": "Xiaoyu Ma",
    "email": "xiaoyuma@google.com",
    "time": "Thu Nov 30 07:48:52 2017 -0800"
  },
  "committer": {
    "name": "Gabe Black",
    "email": "gabeblack@google.com",
    "time": "Fri Jan 12 00:57:56 2018 +0000"
  },
  "message": "sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().\n\nBefore this CL, the addTwoLevelCacheHierarchy() function uses the\ndefault L2XBar class as the interconnect between CPU L1 caches and\nL2. This CL allows passing a user-defined bus to overwrite the\ndefault L2XBar by adding an optional argument to the function.\n\nChange-Id: I917657272fd4924ee0bed882a226851afba26847\nReviewed-on: https://gem5-review.googlesource.com/7364\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c100f0ed5b5d701102ab5ba61e02ad704ee3cac7",
      "old_mode": 33188,
      "old_path": "src/cpu/BaseCPU.py",
      "new_id": "3e82daf2952dbef13b899063e8f779886345d222",
      "new_mode": 33188,
      "new_path": "src/cpu/BaseCPU.py"
    }
  ]
}