tree 1bc429aa1896dea5167e37000428d157b1a0b710
parent 98cbcbb54f56475759fae747b60e47568617640f
author Robert <robert.scheffel1@tu-dresden.de> 1520947740 +0100
committer Robert Scheffel <robert.scheffel1@tu-dresden.de> 1531135031 +0000

arch-riscv: enable rudimentary fs simulation

These changes enable a simple binary to be simulated in full system mode.
Additionally, a new fault was implemented.
It is executed once the CPU is initialized.
This fault clears all interrupts and sets the pc to a reset vector.

Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Reviewed-on: https://gem5-review.googlesource.com/9061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>