tree a5e7ed299c1b2094bdae85f6d9ca017223dffdd8
parent 2595fe6b2834fa0af15baf6f5ad4a8f523c838a6
author Alec Roelke <ar4jc@virginia.edu> 1519010924 -0500
committer Alec Roelke <alec.roelke@gmail.com> 1532803710 +0000

arch-riscv: Add support for trap value register

RISC-V has a set of CSRs that contain information about a trap that was
taken into each privilegel level, such as illegal instruction bytes or
faulting address.  This patch adds that register, modifies existing
faults to make use of it, and adds a new fault for future use with
handling page faults and bad addresses.

Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551
Reviewed-on: https://gem5-review.googlesource.com/11135
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>