# -*- mode:python -*-

# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert

Import('*')

SimObject('CommMonitor.py')
Source('comm_monitor.cc')

SimObject('AbstractMemory.py')
SimObject('AddrMapper.py')
SimObject('Bridge.py')
SimObject('DRAMCtrl.py')
SimObject('ExternalMaster.py')
SimObject('ExternalSlave.py')
SimObject('MemObject.py')
SimObject('SimpleMemory.py')
SimObject('XBar.py')
SimObject('HMCController.py')
SimObject('SerialLink.py')
SimObject('MemDelay.py')

Source('abstract_mem.cc')
Source('addr_mapper.cc')
Source('bridge.cc')
Source('coherent_xbar.cc')
Source('drampower.cc')
Source('dram_ctrl.cc')
Source('external_master.cc')
Source('external_slave.cc')
Source('mem_object.cc')
Source('mport.cc')
Source('noncoherent_xbar.cc')
Source('packet.cc')
Source('port.cc')
Source('packet_queue.cc')
Source('port_proxy.cc')
Source('physical.cc')
Source('simple_mem.cc')
Source('snoop_filter.cc')
Source('stack_dist_calc.cc')
Source('tport.cc')
Source('xbar.cc')
Source('hmc_controller.cc')
Source('serial_link.cc')
Source('mem_delay.cc')

if env['TARGET_ISA'] != 'null':
    Source('fs_translating_port_proxy.cc')
    Source('se_translating_port_proxy.cc')
    Source('page_table.cc')

if env['HAVE_DRAMSIM']:
    SimObject('DRAMSim2.py')
    Source('dramsim2_wrapper.cc')
    Source('dramsim2.cc')

SimObject('MemChecker.py')
Source('mem_checker.cc')
Source('mem_checker_monitor.cc')

DebugFlag('AddrRanges')
DebugFlag('BaseXBar')
DebugFlag('CoherentXBar')
DebugFlag('NoncoherentXBar')
DebugFlag('SnoopFilter')
CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
                      'SnoopFilter'])

DebugFlag('Bridge')
DebugFlag('CommMonitor')
DebugFlag('DRAM')
DebugFlag('DRAMPower')
DebugFlag('DRAMState')
DebugFlag('ExternalPort')
DebugFlag('LLSC')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
DebugFlag('PacketQueue')
DebugFlag('StackDist')
DebugFlag("DRAMSim2")
DebugFlag('HMCController')
DebugFlag('SerialLink')

DebugFlag("MemChecker")
DebugFlag("MemCheckerMonitor")