)]}'
{
  "commit": "a27ce59a39ec8fa20a3c4e9fa53e9b3db1199e91",
  "tree": "d230b106cca136fba2b559ceb8f17843798eaa69",
  "parents": [
    "76e7aec54256696dfdc9567c7ea325fb07c48ef1"
  ],
  "author": {
    "name": "Alec Roelke",
    "email": "alec.roelke@gmail.com",
    "time": "Sun Jun 10 18:41:34 2018 -0400"
  },
  "committer": {
    "name": "Alec Roelke",
    "email": "alec.roelke@gmail.com",
    "time": "Sat Jul 28 18:49:16 2018 +0000"
  },
  "message": "arch-riscv: Add xret instructions\n\nThis patch adds the uret, sret, and mret instructions for use with\nreturning from user-, supervisor-, and machine-level code, respectively.\nThese instructions read the STATUS register to determine the previous\nprivilege level and modify it to re-enable interrupts at the old\nprivilege level. These instructions can only be executed at the\ncorresponding privilege level or higher.\n\nChange-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9\nReviewed-on: https://gem5-review.googlesource.com/11136\nMaintainer: Alec Roelke \u003calec.roelke@gmail.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Robert Scheffel \u003crobert.scheffel1@tu-dresden.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6d3fdebbea0db4fd73f7190c2fddfc2b3505b9e0",
      "old_mode": 33188,
      "old_path": "src/arch/riscv/faults.hh",
      "new_id": "d9cb44c3d639b8de5370715ab0d01f3740390a3e",
      "new_mode": 33188,
      "new_path": "src/arch/riscv/faults.hh"
    },
    {
      "type": "modify",
      "old_id": "a0e3ad19d06f28c1cfe5c6351176c918b89a84ef",
      "old_mode": 33188,
      "old_path": "src/arch/riscv/isa/decoder.isa",
      "new_id": "0c1d7726c57f290425ccbb3c5afcad40e08a20c9",
      "new_mode": 33188,
      "new_path": "src/arch/riscv/isa/decoder.isa"
    },
    {
      "type": "modify",
      "old_id": "e1d57ee53296eeaa1bd621ef4c2df7b19f85a2f3",
      "old_mode": 33188,
      "old_path": "src/arch/riscv/registers.hh",
      "new_id": "bd95cf8210e570b7717d974ea89a5ef4a41b6f57",
      "new_mode": 33188,
      "new_path": "src/arch/riscv/registers.hh"
    }
  ]
}