# Copyright (c) 2005-2007 The Regents of The University of Michigan
# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# modification, are permitted provided that the following conditions are
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# redistributions in binary form must reproduce the above copyright
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# this software without specific prior written permission.
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from MemObject import MemObject
from m5.params import *
from m5.proxy import *

class RubyTester(MemObject):
    type = 'RubyTester'
    cxx_header = "cpu/testers/rubytest/RubyTester.hh"
    num_cpus = Param.Int("number of cpus / RubyPorts")
    cpuInstDataPort = VectorMasterPort("cpu combo ports to inst & data caches")
    cpuInstPort = VectorMasterPort("cpu ports to only inst caches")
    cpuDataPort = VectorMasterPort("cpu ports to only data caches")
    checks_to_complete = Param.Int(100, "checks to complete")
    deadlock_threshold = Param.Int(50000, "how often to check for deadlock")
    wakeup_frequency = Param.Int(10, "number of cycles between wakeups")
    check_flush = Param.Bool(False, "check cache flushing")
    system = Param.System(Parent.any, "System we belong to")