tree 39efaac59cf4f0d36ee343dbc4d47e82da531882
parent 937ed3a0a26002bc5e015c23ecd805e4e32b2cca
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1510854252 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1512128232 +0000

arm: Enable ns registers access in secure mode

Arm security extension introduced register banking between secure and
non-secure mode. This has been removed in armv8 using AArch64 in EL3,
where the decoded register is by default the non-secure version. Using
non-secure register infos(flags) was preventing secure execution to
access the register with the MRC/MCR at EL1.
The patch updates the following banked registers' flags so that their
non-secure version can be accessed in secure mode:

MISCREG_CSSELR, MISCREG_SCTLR, MISCREG_ACTLR, MISCREG_TTBR0,
MISCREG_TTBR1, MISCREG_TTBCR, MISCREG_DACR, MISCREG_DFSR, MISCREG_IFSR,
MISCREG_ADFSR, MISCREG_AIFSR, MISCREG_DFAR, MISCREG_IFAR, MISCREG_PAR,
MISCREG_PRRR, MISCREG_MAIR0, MISCREG_NMRR, MISCREG_MAIR1,
MISCREG_AMAIR0, MISCREG_AMAIR1, MISCREG_VBAR, MISCREG_CONTEXTIDR,
MISCREG_TPIDRURW, MISCREG_TPIDRURO, MISCREG_TPIDRPRW, MISCREG_CNTP_TVAL,
MISCREG_CNTP_CTL, MISCREG_CNTP_CVAL

For those registers the following permission bits have been set:

MISCREG_PRI_S_RD
MISCREG_PRI_S_WR

Change-Id: Ib881c526e75d69e313f8ef66eb78fc704de6bf59
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6201
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>