[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000

[system]
type=System
children=clk_domain cpu dvfs_handler membus monitor physmem
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[1]

[system.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.clk_domain.voltage_domain

[system.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

[system.cpu]
type=TrafficGen
clk_domain=system.clk_domain
config_file=/work/andsan01/outgoing/gem5/tests/testing/../../tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
default_p_state=UNDEFINED
elastic_req=false
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
progress_check=1000000000
system=system
port=system.monitor.slave

[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000

[system.membus]
type=NoncoherentXBar
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=1
frontend_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
response_latency=2
use_default_range=false
width=16
master=system.physmem.port
slave=system.monitor.master system.system_port

[system.monitor]
type=CommMonitor
bandwidth_bins=20
burst_length_bins=20
clk_domain=system.clk_domain
default_p_state=UNDEFINED
disable_addr_dists=true
disable_bandwidth_hists=false
disable_burst_length_hists=false
disable_itt_dists=false
disable_latency_hists=false
disable_outstanding_hists=false
disable_transaction_hists=false
eventq_index=0
itt_bins=20
itt_max_bin=100000
latency_bins=20
outstanding_bins=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
read_addr_mask=18446744073709551615
sample_period=1000000000
system=system
transaction_bins=20
write_addr_mask=18446744073709551615
master=system.membus.slave[0]
slave=system.cpu.port

[system.physmem]
type=DRAMCtrl
IDD0=0.055
IDD02=0.0
IDD2N=0.032
IDD2N2=0.0
IDD2P0=0.0
IDD2P02=0.0
IDD2P1=0.032
IDD2P12=0.0
IDD3N=0.038
IDD3N2=0.0
IDD3P0=0.0
IDD3P02=0.0
IDD3P1=0.038
IDD3P12=0.0
IDD4R=0.157
IDD4R2=0.0
IDD4W=0.125
IDD4W2=0.0
IDD5=0.235
IDD52=0.0
IDD6=0.02
IDD62=0.0
VDD=1.5
VDD2=0.0
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]