tree 1ab43820091dcf702bf2e7ed083eb27bd3cfb313
parent d3ecb5d406a3dc12c53a20c271db3027b8477c39
author Alec Roelke <ar4jc@virginia.edu> 1510082141 -0500
committer Alec Roelke <ar4jc@virginia.edu> 1511916946 +0000

arch-riscv: Move standard ops out of ISA

This patch removes static portions of the standard instruction types
from the generated ISA code and puts them into arch/riscv/insts. Some
dynamically-generated content is left behind for each individual
instruction's implementation. Also, BranchOp is removed due to its
similarity with ImmOp and ImmOp and UImmOp are joined into a single
templated class, ImmOp<T>.

Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
Reviewed-on: https://gem5-review.googlesource.com/6022
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>