diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc
index 986f1f2..ba898d9 100644
--- a/src/cpu/minor/fetch2.cc
+++ b/src/cpu/minor/fetch2.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014,2016 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -415,6 +415,17 @@
                     dyn_inst->pc = fetch_info.pc;
                     DPRINTF(Fetch, "decoder inst %s\n", *dyn_inst);
 
+                    // Collect some basic inst class stats
+                    if (decoded_inst->isLoad())
+                        loadInstructions++;
+                    else if (decoded_inst->isStore())
+                        storeInstructions++;
+                    else if (decoded_inst->isVector())
+                        vecInstructions++;
+                    else if (decoded_inst->isFloating())
+                        fpInstructions++;
+                    else if (decoded_inst->isInteger())
+                        intInstructions++;
 
                     DPRINTF(Fetch, "Instruction extracted from line %s"
                         " lineWidth: %d output_index: %d inputIndex: %d"
@@ -594,6 +605,37 @@
 }
 
 void
+Fetch2::regStats()
+{
+    using namespace Stats;
+
+    intInstructions
+        .name(name() + ".int_instructions")
+        .desc("Number of integer instructions successfully decoded")
+        .flags(total);
+
+    fpInstructions
+        .name(name() + ".fp_instructions")
+        .desc("Number of floating point instructions successfully decoded")
+        .flags(total);
+
+    vecInstructions
+        .name(name() + ".vec_instructions")
+        .desc("Number of SIMD instructions successfully decoded")
+        .flags(total);
+
+    loadInstructions
+        .name(name() + ".load_instructions")
+        .desc("Number of memory load instructions successfully decoded")
+        .flags(total);
+
+    storeInstructions
+        .name(name() + ".store_instructions")
+        .desc("Number of memory store instructions successfully decoded")
+        .flags(total);
+}
+
+void
 Fetch2::minorTrace() const
 {
     std::ostringstream data;
diff --git a/src/cpu/minor/fetch2.hh b/src/cpu/minor/fetch2.hh
index 33c683b..c66fbd8 100644
--- a/src/cpu/minor/fetch2.hh
+++ b/src/cpu/minor/fetch2.hh
@@ -165,6 +165,13 @@
     std::vector<Fetch2ThreadInfo> fetchInfo;
     ThreadID threadPriority;
 
+    /** Stats */
+    Stats::Scalar intInstructions;
+    Stats::Scalar fpInstructions;
+    Stats::Scalar vecInstructions;
+    Stats::Scalar loadInstructions;
+    Stats::Scalar storeInstructions;
+
   protected:
     /** Get a piece of data to work on from the inputBuffer, or 0 if there
      *  is no data. */
@@ -206,6 +213,8 @@
 
     void minorTrace() const;
 
+    void regStats();
+
     /** Is this stage drained?  For Fetch2, draining is initiated by
      *  Execute halting Fetch1 causing Fetch2 to naturally drain.
      *  Branch predictions are ignored by Fetch1 during halt */
diff --git a/src/cpu/minor/pipeline.cc b/src/cpu/minor/pipeline.cc
index 08dc3db..b5659ac 100644
--- a/src/cpu/minor/pipeline.cc
+++ b/src/cpu/minor/pipeline.cc
@@ -106,6 +106,14 @@
 }
 
 void
+Pipeline::regStats()
+{
+    Ticked::regStats();
+
+    fetch2.regStats();
+}
+
+void
 Pipeline::minorTrace() const
 {
     fetch1.minorTrace();
diff --git a/src/cpu/minor/pipeline.hh b/src/cpu/minor/pipeline.hh
index ca96d50..351af6f 100644
--- a/src/cpu/minor/pipeline.hh
+++ b/src/cpu/minor/pipeline.hh
@@ -128,6 +128,9 @@
 
     void minorTrace() const;
 
+    /** Stats registering */
+    void regStats();
+
     /** Functions below here are BaseCPU operations passed on to pipeline
      *  stages */