commit 2a2c66c16c659af4c3588b6c1646d55c66ad53fe
author Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Nov 10 15:35:26 2017 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Nov 21 14:25:56 2017 +0000
tree 633dd84e28b040febbe2fd2efc7cd0a62dc7f60d
parent d3ec34201c14d551e864372a89ccddb1c255e77a

arch-arm: Fix MSR/MRS disassemble

This patch is fixing the Aarch64 MSR/MRS disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the system register name

Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5861
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>