commit 4d893c215ef82358c62bfbb44dc4fef57c524df0
author Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Nov 15 15:27:35 2017 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Nov 21 14:25:56 2017 +0000
tree 5666e520b295a8f17e79146745d1900b14f0c72a
parent 2a2c66c16c659af4c3588b6c1646d55c66ad53fe

arch-arm: Fix MCR/MRC disassemble

This patch is fixing the Aarch32 MCR/MRC disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the coprocessor register name

Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5862
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>