
---------- Begin Simulation Statistics ----------
sim_seconds                                  2.533112                       # Number of seconds simulated
sim_ticks                                2533112171000                       # Number of ticks simulated
final_tick                               2533112171000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  62365                       # Simulator instruction rate (inst/s)
host_op_rate                                    80247                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2619544402                       # Simulator tick rate (ticks/s)
host_mem_usage                                 400132                       # Number of bytes of host memory used
host_seconds                                   967.00                       # Real time elapsed on the host
sim_insts                                    60307726                       # Number of instructions simulated
sim_ops                                      77599286                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         2560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            795840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9093456                       # Number of bytes read from this memory
system.physmem.bytes_read::total            129429648                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       795840                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          795840                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3782016                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6798088                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           40                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12435                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             142119                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15096804                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59094                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813112                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47190040                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker           1011                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             51                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               314175                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3589836                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51095111                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          314175                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             314175                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1493031                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1190659                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2683690                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1493031                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47190040                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          1011                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            51                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              314175                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4780494                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53778801                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15096804                       # Total number of read requests seen
system.physmem.writeReqs                       813112                       # Total number of write requests seen
system.physmem.cpureqs                         218338                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    966195456                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52039168                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              129429648                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6798088                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      312                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4684                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                943939                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                943442                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                943392                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                944196                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                943979                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                943150                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                943272                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                943868                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                943799                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                943285                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               943215                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               943605                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               943692                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               943079                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               942978                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               943601                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 50831                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 50407                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 50438                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 51151                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 50915                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 50185                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 50277                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 50862                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 51366                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 50899                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                50795                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51181                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51246                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                50711                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                50625                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51223                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                       32505                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2533111047500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                      36                       # Categorize read packet sizes
system.physmem.readPktSize::3                14942208                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  154560                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                 754018                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  59094                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                   1040132                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    981079                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    950271                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3550379                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2676469                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2688032                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2649605                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     60687                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     59175                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                    108699                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                   157561                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                   108201                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    16731                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    16591                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    20063                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    12693                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2576                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2623                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      2658                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      2706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      2730                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      2756                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      2782                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      2805                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      2829                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    32777                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    32730                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    32695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    32647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    32623                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    32597                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    32571                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    32548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    32524                       # What write queue length does an incoming req see
system.physmem.totQLat                   393223335500                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              485617965500                       # Sum of mem lat for all requests
system.physmem.totBusLat                  75482460000                       # Total cycles spent in databus access
system.physmem.totBankLat                 16912170000                       # Total cycles spent in bank access
system.physmem.avgQLat                       26047.33                       # Average queueing delay per request
system.physmem.avgBankLat                     1120.27                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  32167.60                       # Average memory access latency
system.physmem.avgRdBW                         381.43                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          20.54                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  51.10                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   2.68                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.14                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.19                       # Average read queue length over time
system.physmem.avgWrQLen                        11.09                       # Average write queue length over time
system.physmem.readRowHits                   15020204                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    793057                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.49                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  97.53                       # Row buffer hit rate for writes
system.physmem.avgGap                       159215.87                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                14674954                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11760315                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            703452                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9798337                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7946170                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             81.097129                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1399969                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              72392                       # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     51400725                       # DTB read hits
system.cpu.dtb.read_misses                      64230                       # DTB read misses
system.cpu.dtb.write_hits                    11699827                       # DTB write hits
system.cpu.dtb.write_misses                     15817                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     3560                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      2361                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    419                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                      1347                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 51464955                       # DTB read accesses
system.cpu.dtb.write_accesses                11715644                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          63100552                       # DTB hits
system.cpu.dtb.misses                           80047                       # DTB misses
system.cpu.dtb.accesses                      63180599                       # DTB accesses
system.cpu.itb.inst_hits                     12329192                       # ITB inst hits
system.cpu.itb.inst_misses                      11376                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2472                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      2865                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 12340568                       # ITB inst accesses
system.cpu.itb.hits                          12329192                       # DTB hits
system.cpu.itb.misses                           11376                       # DTB misses
system.cpu.itb.accesses                      12340568                       # DTB accesses
system.cpu.numCycles                        471811908                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           30566850                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       96025902                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    14674954                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9346139                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      21161280                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 5294268                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     122956                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               95541161                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2622                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         86967                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       195337                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          356                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  12325832                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                900070                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    5461                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          151313220                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.785216                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.150211                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                130167339     86.03%     86.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1302330      0.86%     86.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1712200      1.13%     88.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2496857      1.65%     89.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2222542      1.47%     91.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1109034      0.73%     91.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  2758411      1.82%     93.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                   745566      0.49%     94.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  8798941      5.82%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            151313220                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.031103                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.203526                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 32523025                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              95170118                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19191132                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                962347                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3466598                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              1956722                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                171732                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              112651707                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                566963                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3466598                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 34464368                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                36692438                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       52511672                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  18154881                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               6023263                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              106120156                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 20539                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 985607                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4064974                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              783                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           110525870                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             485527409                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        485436293                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             91116                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              78390038                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 32135831                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             830318                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         736784                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12149928                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             20332565                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            13516637                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1977838                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2480356                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   97929601                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1983934                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 124328965                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            167666                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        21748794                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     57017345                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         501539                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     151313220                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.821666                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.535351                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           107094975     70.78%     70.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13518793      8.93%     79.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7075318      4.68%     84.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5935233      3.92%     88.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12598116      8.33%     96.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             2801723      1.85%     98.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1697051      1.12%     99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              465636      0.31%     99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              126375      0.08%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       151313220                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   62335      0.71%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      3      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                8363613     94.62%     95.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                413579      4.68%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            363666      0.29%      0.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              58629316     47.16%     47.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                93112      0.07%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                  17      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  4      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc              13      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc           2114      0.00%     47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc           13      0.00%     47.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.53% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             52921084     42.57%     90.09% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            12319626      9.91%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              124328965                       # Type of FU issued
system.cpu.iq.rate                           0.263514                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     8839530                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.071098                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          409034606                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         121678500                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     85964427                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               23410                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              12602                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses        10310                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              132792371                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   12458                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           623186                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4678002                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6260                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        29908                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1784543                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads     34107773                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        892534                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3466598                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                27942266                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                433430                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           100134856                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            201220                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              20332565                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             13516637                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1410804                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 113293                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  3501                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          29908                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         350102                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       268608                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               618710                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             121542985                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              52087637                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2785980                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        221321                       # number of nop insts executed
system.cpu.iew.exec_refs                     64299335                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 11558025                       # Number of branches executed
system.cpu.iew.exec_stores                   12211698                       # Number of stores executed
system.cpu.iew.exec_rate                     0.257609                       # Inst execution rate
system.cpu.iew.wb_sent                      120384508                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      85974737                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  47254500                       # num instructions producing a value
system.cpu.iew.wb_consumers                  88210457                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.182222                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.535702                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        21478461                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1482395                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            534359                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    147846622                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.525881                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.516310                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    120416670     81.45%     81.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     13325889      9.01%     90.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3878179      2.62%     93.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2122601      1.44%     94.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1929203      1.30%     95.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       968068      0.65%     96.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1602055      1.08%     97.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       701521      0.47%     98.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      2902436      1.96%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    147846622                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             60458107                       # Number of instructions committed
system.cpu.commit.committedOps               77749667                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       27386657                       # Number of memory references committed
system.cpu.commit.loads                      15654563                       # Number of loads committed
system.cpu.commit.membars                      403601                       # Number of memory barriers committed
system.cpu.commit.branches                    9961339                       # Number of branches committed
system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  68854898                       # Number of committed integer instructions.
system.cpu.commit.function_calls               991261                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               2902436                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    242323721                       # The number of ROB reads
system.cpu.rob.rob_writes                   202019018                       # The number of ROB writes
system.cpu.timesIdled                         1771597                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       320498688                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   4594329392                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    60307726                       # Number of Instructions Simulated
system.cpu.committedOps                      77599286                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              60307726                       # Number of Instructions Simulated
system.cpu.cpi                               7.823407                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         7.823407                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.127822                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.127822                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                550308715                       # number of integer regfile reads
system.cpu.int_regfile_writes                88462540                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      8334                       # number of floating regfile reads
system.cpu.fp_regfile_writes                     2902                       # number of floating regfile writes
system.cpu.misc_regfile_reads                30122249                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 831893                       # number of misc regfile writes
system.cpu.icache.replacements                 979554                       # number of replacements
system.cpu.icache.tagsinuse                511.616693                       # Cycle average of tags in use
system.cpu.icache.total_refs                 11266265                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 980066                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  11.495415                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             6410377000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     511.616693                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.999251                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.999251                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     11266265                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        11266265                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      11266265                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         11266265                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     11266265                       # number of overall hits
system.cpu.icache.overall_hits::total        11266265                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1059442                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1059442                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1059442                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1059442                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1059442                       # number of overall misses
system.cpu.icache.overall_misses::total       1059442                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  13996692496                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  13996692496                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  13996692496                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  13996692496                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  13996692496                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  13996692496                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     12325707                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     12325707                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     12325707                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     12325707                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     12325707                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     12325707                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.085954                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.085954                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.085954                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.085954                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.085954                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.085954                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13211.381554                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13211.381554                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13211.381554                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13211.381554                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13211.381554                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13211.381554                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         5064                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          802                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               297                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    17.050505                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          802                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79338                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        79338                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        79338                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        79338                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        79338                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        79338                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       980104                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       980104                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       980104                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       980104                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       980104                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       980104                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11377433497                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11377433497                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11377433497                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11377433497                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11377433497                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11377433497                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7555000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7555000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7555000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total      7555000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.079517                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.079517                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.079517                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.079517                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.079517                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.079517                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.394106                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.394106                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.394106                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.394106                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.394106                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.394106                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                 64331                       # number of replacements
system.cpu.l2cache.tagsinuse             51338.673427                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1885045                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                129724                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 14.531197                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          2498168723000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 36938.437105                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker    26.056413                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.000348                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   8154.476716                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   6219.702844                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.563636                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000398                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.124427                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.094905                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.783366                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52232                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10453                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       966649                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       387163                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1416497                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       607765                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       607765                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           40                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           40                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           14                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total           14                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       112922                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       112922                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        52232                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        10453                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       966649                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       500085                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1529419                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        52232                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        10453                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       966649                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       500085                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1529419                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           40                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12328                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        10698                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        23068                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2920                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2920                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133207                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133207                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           40                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12328                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       143905                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        156275                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           40                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12328                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       143905                       # number of overall misses
system.cpu.l2cache.overall_misses::total       156275                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      2857500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       118000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    695307000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    633744500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1332027000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       479000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       479000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6744999000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   6744999000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      2857500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       118000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    695307000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7378743500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8077026000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      2857500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       118000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    695307000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7378743500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8077026000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        52272                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10455                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       978977                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       397861                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1439565                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       607765                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       607765                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2960                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2960                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           17                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total           17                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       246129                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       246129                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        52272                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        10455                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       978977                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       643990                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1685694                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        52272                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        10455                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       978977                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       643990                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1685694                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000765                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000191                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012593                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026889                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.016024                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.986486                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.986486                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.176471                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.176471                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541208                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.541208                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000765                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000191                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012593                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.223458                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.092707                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000765                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000191                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012593                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.223458                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.092707                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71437.500000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        59000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56400.632706                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59239.530753                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 57743.497486                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   164.041096                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   164.041096                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50635.469607                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50635.469607                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71437.500000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        59000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56400.632706                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51275.101630                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51684.696849                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71437.500000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        59000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56400.632706                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51275.101630                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51684.696849                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        59094                       # number of writebacks
system.cpu.l2cache.writebacks::total            59094                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           12                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           61                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           73                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           12                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           61                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           73                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           12                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           61                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           73                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           40                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12316                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10637                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        22995                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2920                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2920                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133207                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133207                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           40                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12316                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       143844                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       156202                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           40                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12316                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143844                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       156202                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2357290                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        93251                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    541399772                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    498823739                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1042674052                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29202920                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29202920                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5084805426                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5084805426                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2357290                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        93251                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    541399772                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5583629165                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6127479478                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2357290                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        93251                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    541399772                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5583629165                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6127479478                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      5080830                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002473267                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007554097                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  26911803456                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  26911803456                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      5080830                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193914276723                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193919357553                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000765                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000191                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012580                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026735                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015974                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.986486                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.986486                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.176471                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.176471                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541208                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541208                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000765                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000191                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012580                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223364                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.092663                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000765                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000191                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012580                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223364                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.092663                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 58932.250000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43959.059110                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46895.152675                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45343.511720                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38172.208863                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38172.208863                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 58932.250000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43959.059110                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38817.254560                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39227.919476                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58932.250000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43959.059110                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38817.254560                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39227.919476                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 643478                       # number of replacements
system.cpu.dcache.tagsinuse                511.992821                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 21510687                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 643990                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  33.402207                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               42245000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.992821                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999986                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999986                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     13758124                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13758124                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      7259035                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        7259035                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       242788                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       242788                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       247600                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       247600                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      21017159                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         21017159                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     21017159                       # number of overall hits
system.cpu.dcache.overall_hits::total        21017159                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       737277                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        737277                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2963328                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2963328                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        13553                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        13553                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data           17                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total           17                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3700605                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3700605                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3700605                       # number of overall misses
system.cpu.dcache.overall_misses::total       3700605                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   9762499000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   9762499000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 104581700226                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 104581700226                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    181087500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    181087500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       257000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       257000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 114344199226                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 114344199226                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 114344199226                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 114344199226                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     14495401                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     14495401                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10222363                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10222363                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256341                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       256341                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       247617                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       247617                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     24717764                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     24717764                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     24717764                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     24717764                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050863                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.050863                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289887                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.289887                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052871                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052871                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000069                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000069                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.149714                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.149714                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.149714                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.149714                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13241.290587                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13241.290587                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35291.975855                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35291.975855                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13361.432893                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13361.432893                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30898.785260                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 30898.785260                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30898.785260                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 30898.785260                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        30275                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        18688                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              2630                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             248                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.511407                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    75.354839                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       607765                       # number of writebacks
system.cpu.dcache.writebacks::total            607765                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       351549                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       351549                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2714318                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2714318                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1341                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         1341                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3065867                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3065867                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3065867                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3065867                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385728                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       385728                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249010                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       249010                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12212                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        12212                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           17                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total           17                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       634738                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       634738                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       634738                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       634738                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4809640000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   4809640000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8195040415                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8195040415                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    141777000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    141777000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       223000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       223000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13004680415                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  13004680415                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13004680415                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  13004680415                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395703000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395703000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  36727476899                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  36727476899                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219123179899                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 219123179899                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026610                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026610                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024359                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024359                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047640                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047640                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000069                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000069                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025679                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025679                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025679                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025679                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12468.993695                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12468.993695                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32910.487189                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32910.487189                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11609.646250                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11609.646250                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20488.265103                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20488.265103                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20488.265103                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20488.265103                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229570022553                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1229570022553                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229570022553                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1229570022553                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    83043                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------