commit 68b6f9c8a1819fdeee737cf369cc6a499b505a6c
author Alec Roelke <ar4jc@virginia.edu> Thu Jul 13 14:24:06 2017 -0400
committer Alec Roelke <ar4jc@virginia.edu> Fri Jul 14 20:29:25 2017 +0000
tree 5e83244b5105e118d9634e88816b8e8531e4f739
parent d72eafa64b4313f30f4c7a25000ff04f5cf30380

riscv: Fix bugs with RISC-V decoder and detailed CPUs

This patch fixes some bugs that were missed with the changes to the
decoder that enabled compatibility with compressed instructions. In
order to accommodate speculation with variable instruction widths, a few
assertions in decoder had to be changed to returning faults as the
specification describes should normally happen.  The rest of these
assertions will be changed in a later patch.

[Remove commented-out debugging line and add clarifying comment to
registerName in utility.hh.]

Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95
Reviewed-on: https://gem5-review.googlesource.com/4041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>