Track the PC of the cache data stored in fetch so it doesn't access memory multiple times if information is already in fetch.
--HG--
extra : convert_revision : 00b160b255e998cf99286bcc21894110c7642624
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 85654ce..0331cf0 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -404,6 +404,9 @@
/** The cache line being fetched. */
uint8_t *cacheData[Impl::MaxThreads];
+ /** The PC of the cacheline that has been loaded. */
+ Addr cacheDataPC[Impl::MaxThreads];
+
/** Size of instructions. */
int instSize;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index de883b5..a430f44 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -517,6 +517,11 @@
// Align the fetch PC so it's at the start of a cache block.
fetch_PC = icacheBlockAlignPC(fetch_PC);
+ // If we've already got the block, no need to try to fetch it again.
+ if (fetch_PC == cacheDataPC[tid]) {
+ return true;
+ }
+
// Setup the memReq to do a read of the first instruction's address.
// Set the appropriate read size and flags as well.
// Build request here.
@@ -550,6 +555,8 @@
Packet::ReadReq, Packet::Broadcast);
data_pkt->dataStatic(cacheData[tid]);
+ cacheDataPC[tid] = fetch_PC;
+
DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
fetchedCacheLines++;
