diff --git a/src/arch/riscv/insts/SConscript b/src/arch/riscv/insts/SConscript
index fe90280..8bedc7b 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -1,5 +1,6 @@
 Import('*')
 
 if env['TARGET_ISA'] == 'riscv':
+    Source('mem.cc')
     Source('standard.cc')
     Source('static_inst.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/bitfields.hh b/src/arch/riscv/insts/bitfields.hh
index d664822..eac070e 100644
--- a/src/arch/riscv/insts/bitfields.hh
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -5,6 +5,9 @@
 
 #define CSRIMM  bits(machInst, 19, 15)
 #define FUNCT12 bits(machInst, 31, 20)
+#define IMM5    bits(machInst, 11, 7)
+#define IMM7    bits(machInst, 31, 25)
+#define IMMSIGN bits(machInst, 31)
 #define OPCODE  bits(machInst, 6, 0)
 
 #endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/insts/mem.cc b/src/arch/riscv/insts/mem.cc
new file mode 100644
index 0000000..862700b
--- /dev/null
+++ b/src/arch/riscv/insts/mem.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2015 RISC-V Foundation
+ * Copyright (c) 2017 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+
+#include "arch/riscv/insts/mem.hh"
+
+#include <sstream>
+#include <string>
+
+#include "arch/riscv/insts/bitfields.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+using namespace std;
+
+namespace RiscvISA
+{
+
+string
+Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    stringstream ss;
+    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+        offset << '(' << registerName(_srcRegIdx[0]) << ')';
+    return ss.str();
+}
+
+string
+Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    stringstream ss;
+    ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " <<
+        offset << '(' << registerName(_srcRegIdx[0]) << ')';
+    return ss.str();
+}
+
+}
diff --git a/src/arch/riscv/insts/mem.hh b/src/arch/riscv/insts/mem.hh
new file mode 100644
index 0000000..514d4d6
--- /dev/null
+++ b/src/arch/riscv/insts/mem.hh
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2015 RISC-V Foundation
+ * Copyright (c) 2017 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+
+#ifndef __ARCH_RISCV_INST_MEM_HH__
+#define __ARCH_RISCV_INST_MEM_HH__
+
+#include <string>
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+class MemInst : public RiscvStaticInst
+{
+  protected:
+    int64_t offset;
+    Request::Flags memAccessFlags;
+
+    MemInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+        : RiscvStaticInst(mnem, _machInst, __opClass), offset(0)
+    {}
+};
+
+class Load : public MemInst
+{
+  protected:
+    using MemInst::MemInst;
+
+    std::string generateDisassembly(
+        Addr pc, const SymbolTable *symtab) const override;
+};
+
+class Store : public MemInst
+{
+  protected:
+    using MemInst::MemInst;
+
+    std::string generateDisassembly(
+        Addr pc, const SymbolTable *symtab) const override;
+};
+
+}
+
+#endif // __ARCH_RISCV_INST_MEM_HH__
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index a6f8816..2761fac 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -48,52 +48,52 @@
         }});
         format CompressedLoad {
             0x1: c_fld({{
-                ldisp = CIMM3 << 3 | CIMM2 << 6;
+                offset = CIMM3 << 3 | CIMM2 << 6;
             }}, {{
                 Fp2_bits = Mem;
             }}, {{
-                EA = Rp1 + ldisp;
+                EA = Rp1 + offset;
             }});
             0x2: c_lw({{
-                ldisp = CIMM2<1:1> << 2 |
-                        CIMM3 << 3 |
-                        CIMM2<0:0> << 6;
+                offset = CIMM2<1:1> << 2 |
+                         CIMM3 << 3 |
+                         CIMM2<0:0> << 6;
             }}, {{
                 Rp2_sd = Mem_sw;
             }}, {{
-                EA = Rp1 + ldisp;
+                EA = Rp1 + offset;
             }});
             0x3: c_ld({{
-                ldisp = CIMM3 << 3 | CIMM2 << 6;
+                offset = CIMM3 << 3 | CIMM2 << 6;
             }}, {{
                 Rp2_sd = Mem_sd;
             }}, {{
-                EA = Rp1 + ldisp;
+                EA = Rp1 + offset;
             }});
         }
         format CompressedStore {
             0x5: c_fsd({{
-                sdisp = CIMM3 << 3 | CIMM2 << 6;
+                offset = CIMM3 << 3 | CIMM2 << 6;
             }}, {{
                 Mem = Fp2_bits;
             }}, {{
-                EA = Rp1 + sdisp;
+                EA = Rp1 + offset;
             }});
             0x6: c_sw({{
-                sdisp = CIMM2<1:1> << 2 |
-                        CIMM3 << 3 |
-                        CIMM2<0:0> << 6;
+                offset = CIMM2<1:1> << 2 |
+                         CIMM3 << 3 |
+                         CIMM2<0:0> << 6;
             }}, {{
                 Mem_uw = Rp2_uw;
             }}, ea_code={{
-                EA = Rp1 + sdisp;
+                EA = Rp1 + offset;
             }});
             0x7: c_sd({{
-                sdisp = CIMM3 << 3 | CIMM2 << 6;
+                offset = CIMM3 << 3 | CIMM2 << 6;
             }}, {{
                     Mem_ud = Rp2_ud;
             }}, {{
-                EA = Rp1 + sdisp;
+                EA = Rp1 + offset;
             }});
         }
     }
@@ -202,12 +202,12 @@
         }
         0x5: JOp::c_j({{
             int64_t offset = CJUMPIMM<3:1> << 1 |
-                          CJUMPIMM<9:9> << 4 |
-                          CJUMPIMM<0:0> << 5 |
-                          CJUMPIMM<5:5> << 6 |
-                          CJUMPIMM<4:4> << 7 |
-                          CJUMPIMM<8:7> << 8 |
-                          CJUMPIMM<6:6> << 10;
+                             CJUMPIMM<9:9> << 4 |
+                             CJUMPIMM<0:0> << 5 |
+                             CJUMPIMM<5:5> << 6 |
+                             CJUMPIMM<4:4> << 7 |
+                             CJUMPIMM<8:7> << 8 |
+                             CJUMPIMM<6:6> << 10;
             if (CJUMPIMM<10:10> > 0)
                 offset |= ~((int64_t)0x7FF);
             NPC = PC + offset;
@@ -251,33 +251,33 @@
         }});
         format CompressedLoad {
             0x1: c_fldsp({{
-                ldisp = CIMM5<4:3> << 3 |
-                        CIMM1 << 5 |
-                        CIMM5<2:0> << 6;
+                offset = CIMM5<4:3> << 3 |
+                         CIMM1 << 5 |
+                         CIMM5<2:0> << 6;
             }}, {{
                 Fc1_bits = Mem;
             }}, {{
-                EA = sp + ldisp;
+                EA = sp + offset;
             }});
             0x2: c_lwsp({{
-                ldisp = CIMM5<4:2> << 2 |
-                        CIMM1 << 5 |
-                        CIMM5<1:0> << 6;
+                offset = CIMM5<4:2> << 2 |
+                         CIMM1 << 5 |
+                         CIMM5<1:0> << 6;
             }}, {{
                 assert(RC1 != 0);
                 Rc1_sd = Mem_sw;
             }}, {{
-                EA = sp + ldisp;
+                EA = sp + offset;
             }});
             0x3: c_ldsp({{
-                ldisp = CIMM5<4:3> << 3 |
-                        CIMM1 << 5 |
-                        CIMM5<2:0> << 6;
+                offset = CIMM5<4:3> << 3 |
+                         CIMM1 << 5 |
+                         CIMM5<2:0> << 6;
             }}, {{
                 assert(RC1 != 0);
                 Rc1_sd = Mem_sd;
             }}, {{
-                EA = sp + ldisp;
+                EA = sp + offset;
             }});
         }
         0x4: decode CFUNCT1 {
@@ -310,28 +310,28 @@
         }
         format CompressedStore {
             0x5: c_fsdsp({{
-                sdisp = CIMM6<5:3> << 3 |
-                        CIMM6<2:0> << 6;
+                offset = CIMM6<5:3> << 3 |
+                         CIMM6<2:0> << 6;
             }}, {{
                 Mem_ud = Fc2_bits;
             }}, {{
-                EA = sp + sdisp;
+                EA = sp + offset;
             }});
             0x6: c_swsp({{
-                sdisp = CIMM6<5:2> << 2 |
-                        CIMM6<1:0> << 6;
+                offset = CIMM6<5:2> << 2 |
+                         CIMM6<1:0> << 6;
             }}, {{
                 Mem_uw = Rc2_uw;
             }}, {{
-                EA = sp + sdisp;
+                EA = sp + offset;
             }});
             0x7: c_sdsp({{
-                sdisp = CIMM6<5:3> << 3 |
-                        CIMM6<2:0> << 6;
+                offset = CIMM6<5:3> << 3 |
+                         CIMM6<2:0> << 6;
             }}, {{
                 Mem = Rc2;
             }}, {{
-                EA = sp + sdisp;
+                EA = sp + offset;
             }});
         }
     }
diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa
index bce76c4..ef5f952 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -33,72 +33,6 @@
 //
 // Memory operation instructions
 //
-output header {{
-    class Load : public RiscvStaticInst
-    {
-      public:
-        /// Displacement for EA calculation (signed).
-        int64_t ldisp;
-
-      protected:
-        /// Memory request flags.  See mem_req_base.hh.
-        Request::Flags memAccessFlags;
-
-        /// Constructor
-        Load(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
-            : RiscvStaticInst(mnem, _machInst, __opClass), ldisp(0)
-        {}
-
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-    };
-
-    class Store : public RiscvStaticInst
-    {
-      public:
-        /// Displacement for EA calculation (signed).
-        int64_t sdisp;
-
-      protected:
-        /// Memory request flags.  See mem_req_base.hh.
-        Request::Flags memAccessFlags;
-
-        /// Constructor
-        Store(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
-            : RiscvStaticInst(mnem, _machInst, __opClass), sdisp(0)
-        {
-            sdisp = IMM5 | (IMM7 << 5);
-            if (IMMSIGN > 0)
-                sdisp |= ~((uint64_t)0xFFF);
-        }
-
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-    };
-
-}};
-
-
-output decoder {{
-    std::string
-    Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-    {
-        std::stringstream ss;
-        ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-            ldisp << '(' << registerName(_srcRegIdx[0]) << ')';
-        return ss.str();
-    }
-
-    std::string
-    Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-    {
-        std::stringstream ss;
-        ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " <<
-            sdisp << '(' << registerName(_srcRegIdx[0]) << ')';
-        return ss.str();
-    }
-}};
-
 def template LoadStoreDeclare {{
     /**
      * Static instruction class for "%(mnemonic)s".
@@ -320,24 +254,24 @@
     }
 }};
 
-def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
+def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}}, mem_flags=[],
         inst_flags=[]) {{
     offset_code = """
-                    ldisp = IMM12;
+                    offset = IMM12;
                     if (IMMSIGN > 0)
-                        ldisp |= ~((uint64_t)0xFFF);
+                        offset |= ~((uint64_t)0xFFF);
                   """
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
         inst_flags, 'Load', exec_template_base='Load')
 }};
 
-def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
+def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[],
         inst_flags=[]) {{
     offset_code = """
-                    sdisp = IMM5 | (IMM7 << 5);
+                    offset = IMM5 | (IMM7 << 5);
                     if (IMMSIGN > 0)
-                        sdisp |= ~((uint64_t)0xFFF);
+                        offset |= ~((uint64_t)0xFFF);
                   """
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa
index cd43996..0723620 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -42,6 +42,7 @@
 #include <tuple>
 #include <vector>
 
+#include "arch/riscv/insts/mem.hh"
 #include "arch/riscv/insts/standard.hh"
 #include "arch/riscv/insts/static_inst.hh"
 #include "arch/riscv/insts/unknown.hh"