tree 71ba0ac50a066504c9df48cde18ba65f2da05689
parent 19ad3c4ae46426e988602d870dc2c27fee1154f1
author Alec Roelke <ar4jc@virginia.edu> 1510085996 -0500
committer Alec Roelke <ar4jc@virginia.edu> 1511917103 +0000

arch-riscv: Move parts of mem insts out of ISA

This patch moves static portions of the memory instructions out of the
ISA generated code and puts them into arch/riscv/insts.  It also
simplifies the definitions of load and store instructions by giving
them a common base class.

Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803
Reviewed-on: https://gem5-review.googlesource.com/6024
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>