arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly
This patch fixes the disassembly of AArch64 Exception Generating
instructions, which were not printing the encoded immediate field. This
has been accomplished by changing their underlying type to a newly
defined one.
Change-Id: If58ae3e620d2baa260e12ecdc850225adfcf1ee5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8368
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index b40de02..edc916d 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2013,2017 ARM Limited
+ * Copyright (c) 2011-2013,2017-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -40,6 +40,15 @@
#include "arch/arm/insts/misc64.hh"
std::string
+ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss, "", false);
+ ccprintf(ss, "#0x%x", imm);
+ return ss.str();
+}
+
+std::string
RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 384d946..3b13476 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2013,2017 ARM Limited
+ * Copyright (c) 2011-2013,2017-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -42,6 +42,19 @@
#include "arch/arm/insts/static_inst.hh"
+class ImmOp64 : public ArmStaticInst
+{
+ protected:
+ uint64_t imm;
+
+ ImmOp64(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass, uint64_t _imm) :
+ ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
class RegRegImmImmOp64 : public ArmStaticInst
{
protected:
diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa
index f39a1a5..68f6006 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -242,21 +242,25 @@
(ConditionCode)(uint8_t)(bits(machInst, 3, 0));
return new BCond64(machInst, imm, condCode);
} else if (bits(machInst, 25, 24) == 0x0) {
+
if (bits(machInst, 4, 2))
return new Unknown64(machInst);
+
+ auto imm16 = bits(machInst, 20, 5);
uint8_t decVal = (bits(machInst, 1, 0) << 0) |
(bits(machInst, 23, 21) << 2);
+
switch (decVal) {
case 0x01:
- return new Svc64(machInst);
+ return new Svc64(machInst, imm16);
case 0x02:
- return new Hvc64(machInst);
+ return new Hvc64(machInst, imm16);
case 0x03:
- return new Smc64(machInst);
+ return new Smc64(machInst, imm16);
case 0x04:
- return new Brk64(machInst);
+ return new Brk64(machInst, imm16);
case 0x08:
- return new Hlt64(machInst);
+ return new Hlt64(machInst, imm16);
case 0x15:
return new FailUnimplemented("dcps1", machInst);
case 0x16:
diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa
index faac5cf..cf82ea3 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -42,11 +42,11 @@
fault = std::make_shared<SupervisorCall>(machInst, bits(machInst, 20, 5));
'''
- svcIop = InstObjParams("svc", "Svc64", "ArmStaticInst",
+ svcIop = InstObjParams("svc", "Svc64", "ImmOp64",
svcCode, ["IsSyscall", "IsNonSpeculative",
"IsSerializeAfter"])
- header_output = BasicDeclare.subst(svcIop)
- decoder_output = BasicConstructor64.subst(svcIop)
+ header_output = ImmOp64Declare.subst(svcIop)
+ decoder_output = ImmOp64Constructor.subst(svcIop)
exec_output = BasicExecute.subst(svcIop)
hvcCode = '''
@@ -60,11 +60,11 @@
}
'''
- hvcIop = InstObjParams("hvc", "Hvc64", "ArmStaticInst",
+ hvcIop = InstObjParams("hvc", "Hvc64", "ImmOp64",
hvcCode, ["IsSyscall", "IsNonSpeculative",
"IsSerializeAfter"])
- header_output += BasicDeclare.subst(hvcIop)
- decoder_output += BasicConstructor64.subst(hvcIop)
+ header_output += ImmOp64Declare.subst(hvcIop)
+ decoder_output += ImmOp64Constructor.subst(hvcIop)
exec_output += BasicExecute.subst(hvcIop)
# @todo: extend to take into account Virtualization.
@@ -79,10 +79,10 @@
}
'''
- smcIop = InstObjParams("smc", "Smc64", "ArmStaticInst",
+ smcIop = InstObjParams("smc", "Smc64", "ImmOp64",
smcCode, ["IsNonSpeculative", "IsSerializeAfter"])
- header_output += BasicDeclare.subst(smcIop)
- decoder_output += BasicConstructor64.subst(smcIop)
+ header_output += ImmOp64Declare.subst(smcIop)
+ decoder_output += ImmOp64Constructor.subst(smcIop)
exec_output += BasicExecute.subst(smcIop)
def subst(templateBase, iop):
@@ -169,10 +169,10 @@
bits(machInst, 20, 5));
'''
- brkIop = InstObjParams("brk", "Brk64", "ArmStaticInst",
+ brkIop = InstObjParams("brk", "Brk64", "ImmOp64",
brkCode, ["IsSerializeAfter"])
- header_output += BasicDeclare.subst(brkIop)
- decoder_output += BasicConstructor64.subst(brkIop)
+ header_output += ImmOp64Declare.subst(brkIop)
+ decoder_output += ImmOp64Constructor.subst(brkIop)
exec_output += BasicExecute.subst(brkIop)
hltCode = '''
@@ -188,9 +188,9 @@
'''
- hltIop = InstObjParams("hlt", "Hlt64", "ArmStaticInst",
+ hltIop = InstObjParams("hlt", "Hlt64", "ImmOp64",
hltCode, ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(hltIop)
- decoder_output += BasicConstructor64.subst(hltIop)
+ header_output += ImmOp64Declare.subst(hltIop)
+ decoder_output += ImmOp64Constructor.subst(hltIop)
exec_output += BasicExecute.subst(hltIop)
}};
diff --git a/src/arch/arm/isa/templates/misc64.isa b/src/arch/arm/isa/templates/misc64.isa
index 48d5c64..3811cb5 100644
--- a/src/arch/arm/isa/templates/misc64.isa
+++ b/src/arch/arm/isa/templates/misc64.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2011,2017 ARM Limited
+// Copyright (c) 2011,2017-2018 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -37,6 +37,26 @@
//
// Authors: Gabe Black
+def template ImmOp64Declare {{
+class %(class_name)s : public %(base_class)s
+{
+ protected:
+ public:
+ // Constructor
+ %(class_name)s(ExtMachInst machInst,uint64_t _imm);
+
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+};
+}};
+
+def template ImmOp64Constructor {{
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
+ {
+ %(constructor)s;
+ }
+}};
+
def template RegRegImmImmOp64Declare {{
class %(class_name)s : public %(base_class)s
{
