tree 257b857eda172dde3fe86d19b1d23bffffed256e
parent 8e17f07c295cec854d89cbf427bbd2f8dd915eda
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1516810298 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1518773573 +0000

arch-arm: IMPLEMENTATION DEFINED register

A new pseudo register has been added to the Misc pool. It is the
implementation defined register. This kinds of registers are covered by
the architecture and must be treated differently than UNIMPLEMENTED
registers: their access can be trapped to EL2 (See HCR.TIDCP bit in the
arm arm).
Some previously undecoded registers in c9,c10,c11 have now this register
type.

Change-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7922
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>