997fc505a8b2ed843f2c87bd2371e6510f731324 - arm/gem5

commit	997fc505a8b2ed843f2c87bd2371e6510f731324	[log] [tgz]
author	Steve Reinhardt <stever@eecs.umich.edu>	Wed Feb 07 10:53:37 2007 -0800
committer	Steve Reinhardt <stever@eecs.umich.edu>	Wed Feb 07 10:53:37 2007 -0800
tree	5dd0911a77a2f36e6ee2b9dffc9af68783739134
parent	23d970e6b91158350c1ef694f26d24851e7c34c5 [diff]

Make memory commands dense again to avoid cache stat table explosion.
Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.

--HG--
extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b

src/cpu/memtest/memtest.cc[diff]
src/cpu/o3/fetch_impl.hh[diff]
src/cpu/o3/lsq_unit.hh[diff]
src/cpu/o3/lsq_unit_impl.hh[diff]
src/cpu/simple/atomic.cc[diff]
src/cpu/simple/timing.cc[diff]
src/dev/io_device.hh[diff]
src/mem/cache/base_cache.cc[diff]
src/mem/cache/base_cache.hh[diff]
src/mem/cache/cache_impl.hh[diff]
src/mem/cache/coherence/coherence_protocol.cc[diff]
src/mem/cache/coherence/coherence_protocol.hh[diff]
src/mem/cache/coherence/simple_coherence.hh[diff]
src/mem/cache/coherence/uni_coherence.cc[diff]
src/mem/cache/coherence/uni_coherence.hh[diff]
src/mem/cache/miss/blocking_buffer.cc[diff]
src/mem/cache/miss/blocking_buffer.hh[diff]
src/mem/cache/miss/miss_buffer.hh[diff]
src/mem/cache/miss/miss_queue.cc[diff]
src/mem/cache/miss/miss_queue.hh[diff]
src/mem/cache/miss/mshr.cc[diff]
src/mem/cache/miss/mshr.hh[diff]
src/mem/cache/miss/mshr_queue.cc[diff]
src/mem/cache/miss/mshr_queue.hh[diff]
src/mem/cache/prefetch/base_prefetcher.cc[diff]
src/mem/cache/tags/iic.cc[diff]
src/mem/packet.cc[diff]
src/mem/packet.hh[diff]
src/mem/port.cc[diff]
src/mem/port.hh[diff]
src/mem/tport.cc[diff]

31 files changed

tree: 5dd0911a77a2f36e6ee2b9dffc9af68783739134

build_opts/
configs/
ext/
src/
tests/
util/
AUTHORS
LICENSE
README
RELEASE_NOTES
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