commit c0875dfc398780a05dec68bbe36a17f73a98e030
author Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> Tue Jul 18 16:31:38 2017 +0100
committer Andreas Sandberg <andreas.sandberg@arm.com> Wed Jul 19 10:01:15 2017 +0000
tree 55af0f398cbd2dcd08d6cd3b5c3dd8ff65a85fb6
parent db522eb930020a7a9caf1ea6e289fc81a0bcc842

cpu: Add missing rename of vector registers in the O3 CPU

The introduction of a new vector register class broke rename in the O3
CPU due to an unhandled register class in
DefaultRename<Impl>::renameSrcRegs(). This patch fixes adds the
necessary handling to avoid a panic when the vector register file is
used.

Change-Id: Ie380ab35ec4a151db15402f25b25b58931ee0581
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4140
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>