# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Authors: Ron Dreslinski

import m5
from m5.objects import *
m5.AddToPath('../configs/common')

nb_cores = 4
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]

import ruby_config
ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)

# system simulated
system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())

for cpu in cpus:
    cpu.connectMemPorts(system.membus)
    cpu.clock = '2GHz'

# connect memory to membus
system.physmem.port = system.membus.port


# -----------------------
# run simulation
# -----------------------

root = Root(system = system)
root.system.mem_mode = 'timing'