d857faf073895dcfde97141bd6346fe5d4317f8e - arm/gem5

commit	d857faf073895dcfde97141bd6346fe5d4317f8e	[log] [tgz]
author	Lisa Hsu <hsul@eecs.umich.edu>	Sun Nov 02 21:57:07 2008 -0500
committer	Lisa Hsu <hsul@eecs.umich.edu>	Sun Nov 02 21:57:07 2008 -0500
tree	bfcd9fadba95b409721597948dd46cfda3744ee0
parent	67fda02dda290d614de233846fee434b3713b1dc [diff]

Add in Context IDs to the simulator.  From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId().  The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.

src/arch/alpha/locked_mem.hh[diff]
src/arch/mips/locked_mem.hh[diff]
src/arch/sparc/ua2005.cc[diff]
src/arch/x86/tlb.cc[diff]
src/cpu/base.cc[diff]
src/cpu/base_dyn_inst.hh[diff]
src/cpu/checker/cpu_impl.hh[diff]
src/cpu/o3/cpu.cc[diff]
src/cpu/o3/fetch_impl.hh[diff]
src/cpu/o3/lsq.hh[diff]
src/cpu/o3/lsq_impl.hh[diff]
src/cpu/o3/thread_context.hh[diff]
src/cpu/o3/thread_context_impl.hh[diff]
src/cpu/ozone/cpu_impl.hh[diff]
src/cpu/ozone/front_end_impl.hh[diff]
src/cpu/simple/atomic.cc[diff]
src/cpu/simple/timing.cc[diff]
src/cpu/simple_thread.cc[diff]
src/cpu/thread_context.cc[diff]
src/cpu/thread_context.hh[diff]
src/cpu/thread_state.hh[diff]
src/dev/alpha/backdoor.cc[diff]
src/dev/alpha/tsunami_cchip.cc[diff]
src/dev/mips/malta_cchip.cc[diff]
src/dev/sinic.cc[diff]
src/dev/sparc/iob.cc[diff]
src/mem/cache/blk.hh[diff]
src/mem/cache/prefetch/base.cc[diff]
src/mem/cache/prefetch/ghb.cc[diff]
src/mem/cache/prefetch/ghb.hh[diff]
src/mem/cache/prefetch/stride.cc[diff]
src/mem/cache/prefetch/stride.hh[diff]
src/mem/physical.cc[diff]
src/mem/physical.hh[diff]
src/mem/request.hh[diff]
src/sim/system.cc[diff]
src/sim/system.hh[diff]

37 files changed

tree: bfcd9fadba95b409721597948dd46cfda3744ee0

build_opts/
configs/
ext/
src/
tests/
util/
.hgignore
.hgtags
AUTHORS
LICENSE
README
RELEASE_NOTES
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