)]}'
{
  "id": "b38145246173b51e1a53141fb215432f30edcf95",
  "repo": "arm/gem5",
  "revision": "e9f736738d61775cd3b739dbc9f85cbf4f4c135f",
  "path": "src/mem/protocol/MOESI_AMD_Base.slicc"
}