diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index a9031fe..c0b6aa5 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -922,8 +922,7 @@
         if (el == EL0 && !sctlr.dze)
             return false;
     }
-    if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt ||
-        reg == MISCREG_DC_IVAC_Xt) {
+    if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
         SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
         if (el == EL0 && !sctlr.uci)
             return false;
@@ -3557,7 +3556,7 @@
       .writes(1).exceptUserMode();
     InitReg(MISCREG_DC_IVAC_Xt)
       .warnNotFail()
-      .writes(1);
+      .writes(1).exceptUserMode();
     InitReg(MISCREG_DC_ISW_Xt)
       .warnNotFail()
       .writes(1).exceptUserMode();