| # Copyright (c) 2015 ARM Limited |
| # All rights reserved. |
| # |
| # The license below extends only to copyright in the software and shall |
| # not be construed as granting a license to any other intellectual |
| # property including but not limited to intellectual property relating |
| # to a hardware implementation of the functionality of the software |
| # licensed hereunder. You may use the software subject to the license |
| # terms below provided that you ensure that this notice is replicated |
| # unmodified and in its entirety in all distributions of the software, |
| # modified or unmodified, in source code or in binary form. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
| # contributors may be used to endorse or promote products derived from |
| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| # |
| # Authors: Radhika Jagtap |
| |
| # Basic elastic traces replay script that configures a Trace CPU |
| |
| import optparse |
| |
| from m5.util import addToPath, fatal |
| |
| addToPath('../') |
| |
| from common import Options |
| from common import Simulation |
| from common import CacheConfig |
| from common import MemConfig |
| from common.Caches import * |
| |
| parser = optparse.OptionParser() |
| Options.addCommonOptions(parser) |
| |
| if '--ruby' in sys.argv: |
| print "This script does not support Ruby configuration, mainly"\ |
| " because Trace CPU has been tested only with classic memory system" |
| sys.exit(1) |
| |
| (options, args) = parser.parse_args() |
| |
| if args: |
| print "Error: script doesn't take any positional arguments" |
| sys.exit(1) |
| |
| numThreads = 1 |
| |
| if options.cpu_type != "TraceCPU": |
| fatal("This is a script for elastic trace replay simulation, use "\ |
| "--cpu-type=TraceCPU\n"); |
| |
| if options.num_cpus > 1: |
| fatal("This script does not support multi-processor trace replay.\n") |
| |
| # In this case FutureClass will be None as there is not fast forwarding or |
| # switching |
| (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) |
| CPUClass.numThreads = numThreads |
| |
| system = System(cpu = CPUClass(cpu_id=0), |
| mem_mode = test_mem_mode, |
| mem_ranges = [AddrRange(options.mem_size)], |
| cache_line_size = options.cacheline_size) |
| |
| # Create a top-level voltage domain |
| system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) |
| |
| # Create a source clock for the system. This is used as the clock period for |
| # xbar and memory |
| system.clk_domain = SrcClockDomain(clock = options.sys_clock, |
| voltage_domain = system.voltage_domain) |
| |
| # Create a CPU voltage domain |
| system.cpu_voltage_domain = VoltageDomain() |
| |
| # Create a separate clock domain for the CPUs. In case of Trace CPUs this clock |
| # is actually used only by the caches connected to the CPU. |
| system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, |
| voltage_domain = |
| system.cpu_voltage_domain) |
| |
| # All cpus belong to a common cpu_clk_domain, therefore running at a common |
| # frequency. |
| for cpu in system.cpu: |
| cpu.clk_domain = system.cpu_clk_domain |
| |
| # BaseCPU no longer has default values for the BaseCPU.isa |
| # createThreads() is needed to fill in the cpu.isa |
| for cpu in system.cpu: |
| cpu.createThreads() |
| |
| # Assign input trace files to the Trace CPU |
| system.cpu.instTraceFile=options.inst_trace_file |
| system.cpu.dataTraceFile=options.data_trace_file |
| |
| # Configure the classic memory system options |
| MemClass = Simulation.setMemClass(options) |
| system.membus = SystemXBar() |
| system.system_port = system.membus.slave |
| CacheConfig.config_cache(options, system) |
| MemConfig.config_mem(options, system) |
| |
| root = Root(full_system = False, system = system) |
| Simulation.run(options, root, system, FutureClass) |