)]}' { "log": [ { "commit": "1d4717ab7ece153206b0bd0bd8e1acc9497cbf05", "tree": "d2f70fe360e8fc7470cfe0090290e8aa47bd48c8", "parents": [ "e5d98f6e638455c81a4fba63492e4bbaf1cd7db1" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Mon Oct 31 15:52:15 2016 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Fri Mar 02 18:41:13 2018 +0000" }, "message": "mem-cache: Remove mumBlock redundant initialiation from FALRU\n\nChange-Id: Id3afec0a62446d6d0f44ccb655032343037637e0\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8281\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "e5d98f6e638455c81a4fba63492e4bbaf1cd7db1", "tree": "78043df6bc1f62ce3d2e0b4f116140fdd1335a4d", "parents": [ "1ecc7a8c776bacd04c109cc286e569d434497229" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Tue Nov 22 11:38:57 2016 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Fri Mar 02 16:18:29 2018 +0000" }, "message": "mem-cache: Populate the secure bit when the temp block is filled\n\nThe secure bit should be set when we fill a block with data from a\nsecure location, as indicated by the packet that triggers the fill.\nThis patch fixes a bug in which the cache wouldn\u0027t populate the secure\nbit when filling the temp block.\n\nChange-Id: I95c706146449804ff42b205b25dd79750f3e882a\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8284\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\n" }, { "commit": "1ecc7a8c776bacd04c109cc286e569d434497229", "tree": "9db50dd68776df0c81c58bf3264edfa40bd0d176", "parents": [ "d7de6dff7707ac48303231ee4a4f5790f9495304" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Nov 02 17:29:42 2016 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Fri Mar 02 16:17:44 2018 +0000" }, "message": "mem-cache: Remove unnecessary block initialization on writeback\n\nChange-Id: Ia9b825bcbb8d326705f74c15a93a88703153ba5a\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8283\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\n" }, { "commit": "d7de6dff7707ac48303231ee4a4f5790f9495304", "tree": "a488c9488745b9fa273879d786b5be321ced60a9", "parents": [ "2a714355506200d281175e49f3a5c7886ce3df7d" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Mon Feb 05 11:38:32 2018 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Fri Mar 02 16:16:17 2018 +0000" }, "message": "configs: Fix L3Cache instantiation in lat_mem_rd.py\n\nThis changeset updates the lat_mem_rd.py to configure the L3Cache\nusing the split tag_latency, data_latency parameters.\n\nChange-Id: I8bc41d5f7664111bdda0972356d1a17762aa77e5\nReviewed-on: https://gem5-review.googlesource.com/8288\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\n" }, { "commit": "2a714355506200d281175e49f3a5c7886ce3df7d", "tree": "be090ad90670f3a1eb1f451a12b086c738a8c3fa", "parents": [ "3c076e4d69b38be9e4ce7ca9cfb7145ae6f27393" ], "author": { "name": "Daniel R. Carvalho", "email": "odanrc@yahoo.com.br", "time": "Tue Feb 27 14:31:59 2018 +0100" }, "committer": { "name": "Daniel Carvalho", "email": "odanrc@yahoo.com.br", "time": "Thu Mar 01 09:40:06 2018 +0000" }, "message": "mem-cache: Remove extra block init in BaseSetAssoc\n\nRemoved extra initialization of cache block just after they have been\ncreated and organized the comments.\n\nChange-Id: I75c1beaf0489e3e530fd8cbff2739dc7593e3e6f\nReviewed-on: https://gem5-review.googlesource.com/8661\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "3c076e4d69b38be9e4ce7ca9cfb7145ae6f27393", "tree": "5e0ceaa3782b22db7fa01e521955be3b01f915ad", "parents": [ "f4d83eaf52926aa379292a9f75ba6b36eb04c52d" ], "author": { "name": "Daniel R. Carvalho", "email": "odanrc@yahoo.com.br", "time": "Mon Feb 26 15:22:33 2018 +0100" }, "committer": { "name": "Daniel Carvalho", "email": "odanrc@yahoo.com.br", "time": "Thu Mar 01 08:14:33 2018 +0000" }, "message": "mem-cache: Vectorize C arrays in BaseSetAssoc.\n\nTransform BaseSetAssoc\u0027s arrays into C++ vectors to avoid unnecessary\nresource management.\n\nChange-Id: I656f42f29e5f9589eba491b410ca1df5a64f2f34\nReviewed-on: https://gem5-review.googlesource.com/8621\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "f4d83eaf52926aa379292a9f75ba6b36eb04c52d", "tree": "63e9ce7104671974908bdd294cd04fcb71c6f58e", "parents": [ "ed0f02e1f68e8771f4de514716f34c3de32b3045" ], "author": { "name": "Anouk Van Laer", "email": "anouk.vanlaer@arm.com", "time": "Mon Aug 21 16:02:45 2017 +0100" }, "committer": { "name": "Anouk Van Laer", "email": "anouk.vanlaer@arm.com", "time": "Wed Feb 28 21:56:08 2018 +0000" }, "message": "sim, power: Temperature used for power calculations\n\nThe temperature used for the power calculations was fixed at 0\ndegrees, unless a thermal model was setup. This commit allows\nthe user to set the temperature that needs to be used by the\npower calculation during gem5 configuration. This value will be\noverwritten if there are thermal models present.\n\nChange-Id: I7ca8fa6766bdcba9d362c12fc75d1e1f74385f35\nReviewed-by: Sascha Bischoff \u003csascha.bischoff@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8602\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "ed0f02e1f68e8771f4de514716f34c3de32b3045", "tree": "b9dafb62a24ee3e7c876c255b245123a736c2ab2", "parents": [ "fbe63074e3a8128bdbe1a5e8f6509c565a3abbd4" ], "author": { "name": "Anouk Van Laer", "email": "anouk.vanlaer@arm.com", "time": "Wed Mar 01 17:05:18 2017 +0000" }, "committer": { "name": "Anouk Van Laer", "email": "anouk.vanlaer@arm.com", "time": "Wed Feb 28 21:55:35 2018 +0000" }, "message": "sim: Added model type to power model\n\nStatic, dynamic or all to differentiate between types of power models\nso for example static models will not be asked for a dynamic power\n\nChange-Id: I3a0385821f7c671aedddaebeb038c677367faa81\nReviewed-by: Sascha Bischoff \u003csascha.bischoff@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8601\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "fbe63074e3a8128bdbe1a5e8f6509c565a3abbd4", "tree": "d2d117b1e7c929a4c83b0f41dd9f471c08e82567", "parents": [ "e83f27eb31144439f832c79bb380e69e957d2949" ], "author": { "name": "Daniel R. Carvalho", "email": "odanrc@yahoo.com.br", "time": "Fri Feb 23 15:55:06 2018 +0100" }, "committer": { "name": "Daniel Carvalho", "email": "odanrc@yahoo.com.br", "time": "Sat Feb 24 15:54:57 2018 +0000" }, "message": "mem-cache: Fix CacheSet memory leak\n\nCacheSet blocks were being allocated but never freed.\nUsed vector to avoid using pure C array.\n\nChange-Id: I6f32fa5a305ff4e1d7602535026c1396764102ed\nReviewed-on: https://gem5-review.googlesource.com/8603\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "e83f27eb31144439f832c79bb380e69e957d2949", "tree": "a16fdce1e4a26e73ce72d0312834041fe100d1fc", "parents": [ "38a1e23c3910aa10c41478ba1715f50c4b4a8ac2" ], "author": { "name": "Khalique", "email": "khalique913@gmail.com", "time": "Thu Feb 22 13:19:40 2018 -0600" }, "committer": { "name": "Khalique Ahmed", "email": "khalique913@gmail.com", "time": "Sat Feb 24 00:28:29 2018 +0000" }, "message": "sparc: Fix FS Checkpoint loading\n\nProposed changes to SPARC FS simulation, testing indicates that checkpoints are now loaded correctly with the following command: build/SPARC/gem5.opt configs/example/fs.py -r 1\n\nChange-Id: Icd44f01a74c41a78828ef6fd7b661e584bdb6966\nReviewed-on: https://gem5-review.googlesource.com/8581\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "38a1e23c3910aa10c41478ba1715f50c4b4a8ac2", "tree": "f3b78e8a49fb46e1b99246cc8976c08382804215", "parents": [ "73dcf05f633b5e3a7d9a16338a64c1832ef38388" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Feb 15 09:55:20 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 20 13:30:02 2018 +0000" }, "message": "arch-arm: Make hlt64 a mem barrier with semihosting\n\nThe HLT instruction is used to trap into semihosting. The semihosting\ncode can change the contents of memory behind the back of the CPU,\nwhich requires instructions triggering semihosting to be\nnon-speculative and memory barriers.\n\nChange-Id: I735166251aa194120ad49c08082d4ac65fe96524\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8373\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "73dcf05f633b5e3a7d9a16338a64c1832ef38388", "tree": "b66442229292c0b699e5ae7f6c1b236648c21a87", "parents": [ "26b03914d7dbcf6b6c8c0a9c08d4e3ff81365376" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 13 14:01:57 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 20 13:30:02 2018 +0000" }, "message": "arch-arm: Add AArch32 HLT Semihosting interface\n\nAArch32 HLT instruction is now able to issue Arm Semihosting commands as\nthe AArch64 counterpart in either Arm and Thumb mode.\n\nChange-Id: I77da73d2e6a9288c704a5f646f4447022517ceb6\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8372\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "26b03914d7dbcf6b6c8c0a9c08d4e3ff81365376", "tree": "67bfd89bd42b5d6fcc9c9dd15e7f6541522dc031", "parents": [ "a7083ece990adddfd3bec8b48c5db7dee1781d55" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 13 13:55:36 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 20 13:30:02 2018 +0000" }, "message": "arch-arm: Add AArch32 SVC Semihosting interface\n\nAArch32 Svc instruction is now able to issue Arm Semihosting commands as\nthe AArch64 counterpart in either Arm and Thumb mode.\n\nChange-Id: Ibe47ac23d0c26f3f819cc0e2b3ee874b5cdbb3d3\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8371\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "a7083ece990adddfd3bec8b48c5db7dee1781d55", "tree": "b969138bafaf25660481fb79328775f1f3641c63", "parents": [ "657d4054ea36e6af8959f2fa7bcfd79b7c887cfd" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Feb 15 09:57:00 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 20 13:30:02 2018 +0000" }, "message": "arch-arm: Adding isa templates for semihosting ops\n\nA new class of Semihosting constructor templates has been added. Their\nmain purpose is to check if the Exception Generation Instructions (HLT,\nSVC) are actually a semihosting command. If that is the case, the\nIsMemBarrier flag is raised, so that in the O3 model we perform a\ncoherent memory access during the semihosting operation.\n\nChange-Id: Ib87fdeb70ee7a930659563230a80cce0e1372c32\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8370\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "657d4054ea36e6af8959f2fa7bcfd79b7c887cfd", "tree": "935336ca8e5bbf1967dc8c41b671738683070daf", "parents": [ "803a8db53aae57d42bd2465c9284df91ed5e7641" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Feb 14 18:42:19 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 20 13:30:02 2018 +0000" }, "message": "arch-arm: HLT using immediate when checking for semihosting\n\nHLT can use the immediate field when checking for semihosting,\nrather than re-parsing it from the machInst variable.\n\nChange-Id: I072cb100029da34d129b90c5d17e1728f9016c88\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8369\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "803a8db53aae57d42bd2465c9284df91ed5e7641", "tree": "ffbc793bf70c643e6f1f686eb5cd8188737000c5", "parents": [ "a3bb33b257324ad9da3e656e30ba61e6f4b5497f" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Feb 14 17:45:38 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 20 13:30:02 2018 +0000" }, "message": "arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly\n\nThis patch fixes the disassembly of AArch64 Exception Generating\ninstructions, which were not printing the encoded immediate field. This\nhas been accomplished by changing their underlying type to a newly\ndefined one.\n\nChange-Id: If58ae3e620d2baa260e12ecdc850225adfcf1ee5\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8368\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "a3bb33b257324ad9da3e656e30ba61e6f4b5497f", "tree": "f96fcfd5b9d68f65af3e62da12a168c3f58a4cc7", "parents": [ "68eb852d62864b2093c365ce2a80e9fd39908312" ], "author": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Tue Feb 13 19:01:17 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 20 13:30:02 2018 +0000" }, "message": "cpu-o3: Don\u0027t add non-speculative mem barriers to the IQ twice\n\nThere are cases where the IEW adds a non-speculative instruction to\nthe IQ twice. This can happen if an instruction is flagged as\nIsMemBarrier and IsNonSpeculative. Avoid adding non-speculative\ninstructions in the IEW to the IQ by checking if it has been added\nalready.\n\nChange-Id: Ifcff676a451b57b2406ce00ed8dae19ed399515f\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Javier Setoain \u003cjavier.setoain@arm.com\u003e\nReviewed-by: Giacomo Gabrielli \u003cgiacomo.gabrielli@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8374\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "68eb852d62864b2093c365ce2a80e9fd39908312", "tree": "1567270cccee68ecb8ba1e6b669286496fdd2dd7", "parents": [ "7352324d4dda31ffb6fb5997e0fe2378c27e96b9" ], "author": { "name": "Brandon Potter", "email": "brandon.potter@amd.com", "time": "Mon Feb 19 13:54:46 2018 -0500" }, "committer": { "name": "Brandon Potter", "email": "Brandon.Potter@amd.com", "time": "Mon Feb 19 23:52:52 2018 +0000" }, "message": "mem: fix page_table bug for .fast build\n\nSince b8b13206c8, the \u0027.fast\u0027 build has failed to compile with an error\ncaused by a variable and an assert.\n\nAs a reminder, assert macros are optimized out of the build for \u0027.fast\u0027.\nIf an assert check requires a variable that is unused anywhere else in\nthe code, the compiler complains that the variable is unused and the\nscons build fails. The solution is to add a M5_VAR_USED specifier to\ntell the compiler to ignore the variable.\n\nChange-Id: I38f6bbed1e4c0506c5bbc1206c21f1f7e3d8dfe6\nReviewed-on: https://gem5-review.googlesource.com/8462\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\n" }, { "commit": "7352324d4dda31ffb6fb5997e0fe2378c27e96b9", "tree": "09842cbeb5d3455fac31fa8c9297b37979fd6de3", "parents": [ "72f15d3b8926432bed4740403d85a76549abb8bb" ], "author": { "name": "Alec Roelke", "email": "ar4jc@virginia.edu", "time": "Mon Feb 19 12:21:33 2018 -0500" }, "committer": { "name": "Alec Roelke", "email": "ar4jc@virginia.edu", "time": "Mon Feb 19 20:31:33 2018 +0000" }, "message": "arch-riscv: Fix compressed branch op offset\n\nThere is a bug in RISC-V\u0027s compressed branch instructions where the\noffsets are not stored in ImmOp\u0027s immediate field, causing incorrect\nbranchTarget() return values. This patch adds a new compressed branch\nop format, CBOp, which correctly stores the offset.\n\nChange-Id: Iac6e9b091d63f3dce4717ee5a9ec31a7cbd6c377\nReviewed-on: https://gem5-review.googlesource.com/8441\nReviewed-by: Tuan Ta \u003cqtt2@cornell.edu\u003e\nMaintainer: Alec Roelke \u003car4jc@virginia.edu\u003e\n" }, { "commit": "72f15d3b8926432bed4740403d85a76549abb8bb", "tree": "5dafe2ab3fd4cdf41c57d190e1c17f3385fa85c0", "parents": [ "3b25b7cc64035b181d139b90abb692f5eda935a5" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Feb 14 14:03:34 2018 +0000" }, "committer": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Mon Feb 19 16:12:25 2018 +0000" }, "message": "arch-arm: Semihosting not available in syscall emulation\n\nArm Semihosting is not available in syscall emulation since we don\u0027t\nhave an Arm system in that scenario. Trying to use it in \"se\" mode will\nmake getArmSystem assertion fail.\n\nChange-Id: I4cf49ae801ec6e6c93134ac6ae2a0f412040684c\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8367\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "3b25b7cc64035b181d139b90abb692f5eda935a5", "tree": "3d7ab1c3bea654735e0be6569062700ad7265887", "parents": [ "7b96fc2456d71d0df2700384ab44c1ed01be2f03" ], "author": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Tue Feb 13 18:03:32 2018 +0000" }, "committer": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Mon Feb 19 14:24:46 2018 +0000" }, "message": "arch-arm: Add support for secure state in semihosting\n\nThe semihosting component currently issues non-secure memory accesses\nusing the standard port proxy. This doesn\u0027t work when the guest is\nrunning in secure state.\n\nChange-Id: Id34b142cfcd9d77b455c040ae7f7397c29aebbc6\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8365\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "7b96fc2456d71d0df2700384ab44c1ed01be2f03", "tree": "912d232864b064dfd0f4d924b56e178a0c2d0dfe", "parents": [ "6039da55d87fb27b149ac3da0ebce41bb55a3bee" ], "author": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Tue Feb 13 18:00:22 2018 +0000" }, "committer": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Mon Feb 19 14:24:46 2018 +0000" }, "message": "mem: Refactor port proxies to support secure accesses\n\nThe current physical port proxy doesn\u0027t know how to tag memory\naccesses as secure. Refactor the class slightly to create a set of\nmethods (readBlobPhys, writeBlobPhys, memsetBlobPhys) that always\naccess physical memory and take a set of Request::Flags as an\nargument. The new port proxy, SecurePortProxy, uses this interface to\nissue secure physical accesses.\n\nChange-Id: I8232a4b35025be04ec8f91a00f0580266bacb338\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8364\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "6039da55d87fb27b149ac3da0ebce41bb55a3bee", "tree": "0accdc76afa3790eb04d878d89e5f5158fd25572", "parents": [ "80427ea030b521779521f57b092bc6b4afc86ab2" ], "author": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Thu Feb 08 20:13:13 2018 +0000" }, "committer": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Mon Feb 19 14:24:46 2018 +0000" }, "message": "arch-arm: Add aarch64 semihosting support\n\nAdd basic support for Arm Semihosting 2.0 simulation calls [1]. These\ncalls let the guest system call a simulator or debugger to request\nOS-like support when running bare metal code.\n\nWith the exception of SYS_SYSTEM, this implementation supports all of\nthe Semihosting 2.0 specification in aarch64.\n\n[1] https://developer.arm.com/docs/100863/latest/preface\n\nChange-Id: I08c153c18a4a4fb9f95d318e2a029724935192a7\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8147\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "80427ea030b521779521f57b092bc6b4afc86ab2", "tree": "257b857eda172dde3fe86d19b1d23bffffed256e", "parents": [ "8e17f07c295cec854d89cbf427bbd2f8dd915eda" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Jan 24 16:11:38 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Feb 16 09:32:53 2018 +0000" }, "message": "arch-arm: IMPLEMENTATION DEFINED register\n\nA new pseudo register has been added to the Misc pool. It is the\nimplementation defined register. This kinds of registers are covered by\nthe architecture and must be treated differently than UNIMPLEMENTED\nregisters: their access can be trapped to EL2 (See HCR.TIDCP bit in the\narm arm).\nSome previously undecoded registers in c9,c10,c11 have now this register\ntype.\n\nChange-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7922\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "8e17f07c295cec854d89cbf427bbd2f8dd915eda", "tree": "474b9791cdbb5920fa3b3ceff107b82d9a62184c", "parents": [ "94553f32d8dbb7979dbeb0e6bafaa5db1985db1e" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Jan 24 15:53:43 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Feb 16 09:32:53 2018 +0000" }, "message": "arch-arm: Arch regs and pseudo regs distinction\n\nA new identifier has been introduced: NUM_PHYS_MISCREGS, which is used\nas a boundary for the number of physical (real) Misc registers in the\nsystem. Pseudo registers (like CP15_UNIMPL) have been moved after the\nNUM_PHYS_MISCREGS identifier, so that their enum number is\n(NUM_PHYS_MISCREGS \u003c number \u003c NUM_MISCREGS). Moving away those\nregisters has created some free slots that can be used for future Misc\nregister implementation.\nSERIALIZE and UNSERIALIZE now only save/restore PHYSICAL Misc Registers.\nThis allows us to define as many pseudo registers as we want without\nbeing concerned about checkpoint compatibility.\n\nChange-Id: I7e297b814eeaa4bee640e81bee625fb66710af45\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7921\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "94553f32d8dbb7979dbeb0e6bafaa5db1985db1e", "tree": "643680b58619faa61bbf173aa549f12cc1e5f730", "parents": [ "c105793a2027cd113233e8ce6c5e2d4ea2f9cded" ], "author": { "name": "Chuan Zhu", "email": "chuan.zhu@arm.com", "time": "Tue Jan 23 10:19:07 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Feb 16 09:29:38 2018 +0000" }, "message": "arch-arm: Fix syntax error in TLB::getResultTe\n\nThe patch fixes one syntax error in TLB::getResultTe\n\nChange-Id: I31a72a52d5c03f43929a69ca1be61d9c20e76f5b\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7983\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "c105793a2027cd113233e8ce6c5e2d4ea2f9cded", "tree": "7e8fd86bc3ea02ea382d451db968ca8f61e9ea9a", "parents": [ "fcc98a50e3af273921914f9adf61db7b1944bb05" ], "author": { "name": "Chuan Zhu", "email": "chuan.zhu@arm.com", "time": "Wed Jul 26 17:03:18 2017 +0100" }, "committer": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Fri Feb 16 09:28:24 2018 +0000" }, "message": "arch-arm: Fix big endian support in {Load,Store}Double64\n\n{Load, Store}Double64 didn\u0027t consider some of the big-endian\nsituations. Added big-endian related data conversions to correct them.\n\nChange-Id: I8840613f94446e6042276779d1f02350ab57987f\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8145\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "fcc98a50e3af273921914f9adf61db7b1944bb05", "tree": "abff11863d45408c0a270c695a038e9f67463f01", "parents": [ "dec0025dea92f78309d17b1840ed8449ac397d8f" ], "author": { "name": "Chuan Zhu", "email": "chuan.zhu@arm.com", "time": "Wed Aug 02 09:52:28 2017 +0100" }, "committer": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Fri Feb 16 09:28:24 2018 +0000" }, "message": "arch-arm: Fix big endian support in do{Long,L1,L2}Descriptor\n\ndo{Long,L1,L2}Descriptor was not able to load descriptors correctly\nfor big-endian situations, causing recognised Descriptors. Added\nbig-endian related data conversions to correct them.\n\nChange-Id: I0fdfbbdf56f94bbed19172acae1b6e4a0382b5a0\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8144\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "dec0025dea92f78309d17b1840ed8449ac397d8f", "tree": "ae0bcec8e5bd48f826132c59ba5deacbd0f734bd", "parents": [ "9c97d3fe691e0cf8da0dfb7fc2198bedd0529b2f" ], "author": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Fri Feb 09 18:26:44 2018 +0000" }, "committer": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Fri Feb 16 09:28:24 2018 +0000" }, "message": "arch-arm: Add support for automatic reset addr selection\n\nAdd an option to automatically set the aarch64 reset vector to the\nentry point of the kernel. This is useful when running bare metal\nworkloads that don\u0027t use a normal boot loader.\n\nChange-Id: Id472f865d461f0d8d8ea8efe5db582c170de0b90\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Giacomo Gabrielli \u003cgiacomo.gabrielli@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8143\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "9c97d3fe691e0cf8da0dfb7fc2198bedd0529b2f", "tree": "3e3741df886ef4a5c70cdbe123fa22d564307302", "parents": [ "a30b0e39efaf14ba8b13cff1ada495d68a2ac01e" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Feb 09 11:07:53 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Feb 16 09:26:43 2018 +0000" }, "message": "arch-arm: Change ArmFault cast from reinterpret to static\n\nChanging casting type in src/arch/arm/isa.cc\n\nChange-Id: Ia19b30a1bf8b1b25df149b52613a3533eaced03a\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8241\nReviewed-by: Brandon Potter \u003cBrandon.Potter@amd.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "a30b0e39efaf14ba8b13cff1ada495d68a2ac01e", "tree": "24e6d9afa72746ffbe08ae81ae74995c316d0f2a", "parents": [ "b78f216c157c763c208d390b609f0cf70bb45576" ], "author": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Thu Feb 08 18:18:16 2018 +0000" }, "committer": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Fri Feb 16 09:25:14 2018 +0000" }, "message": "arch-arm: Decode Brk64 instructions\n\nThe brk instruction in aarch64 was decoded as an unimplemented\ninstruction. Fix that.\n\nChange-Id: I3eb36a016ab56d882426c5cdef3a0b594de0f9cd\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8142\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "b78f216c157c763c208d390b609f0cf70bb45576", "tree": "00298e1cf940585934932a3a9ef4207300fcb62d", "parents": [ "d5231d14af1fbc52c9325b51cacb86bf2fd91686" ], "author": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Fri Feb 09 12:48:37 2018 +0000" }, "committer": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Fri Feb 16 09:25:14 2018 +0000" }, "message": "mem: Add PortProxy read/write helper with explicit endianness\n\nChange-Id: Ia9a11ca68b2892dafd02f2c37324b99b35c77d34\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8146\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "d5231d14af1fbc52c9325b51cacb86bf2fd91686", "tree": "c77656b38ac245cc7a9875c2e34d7a17ab2d958e", "parents": [ "cf58af7cf2402a280d6789797a9bc956209bdc30" ], "author": { "name": "Chuan Zhu", "email": "chuan.zhu@arm.com", "time": "Wed Aug 02 09:52:28 2017 +0100" }, "committer": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Fri Feb 16 09:25:14 2018 +0000" }, "message": "sim: Add gtoh/htog helpers that take an explicit endianness\n\nAdd helper functions to swap between guest byte order and host byte\norder that take a guest endianness as a parameter. These functions are\ncalled htog and htog to be consistent with the helper functions that\nextract guest byte order from a compile time constant.\n\nChange-Id: Ie6be7dfd3b7a58ad6bfb57b25be5f85b5f425929\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8201\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "cf58af7cf2402a280d6789797a9bc956209bdc30", "tree": "6b7197e7a63a20d5b8c05095ffd1a42447759cf8", "parents": [ "8da5e6b8b6fc1665edefffdf36c0aa7b9d53370d" ], "author": { "name": "Chuan Zhu", "email": "chuan.zhu@arm.com", "time": "Tue Jan 02 16:14:33 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Feb 16 09:21:41 2018 +0000" }, "message": "arch-arm: Fix Secure state check in checkFPAdvSIMDTrap64\n\nThe old code does secure state check by using \"el \u003c\u003d EL2\", which\nmis-considers secure EL1 and EL0. This patch fixes this by using\ninSecureState as in ARM ARM.\n\nChange-Id: I01d847c6af022c1462b16206cbc576f15f5569fd\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8081\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "8da5e6b8b6fc1665edefffdf36c0aa7b9d53370d", "tree": "3e452b4d6b3072152bc181fdeeef29f57d168b8c", "parents": [ "4e13495f5d8e1e98609fd67b9b29c67eaeb753fc" ], "author": { "name": "Rico Amslinger", "email": "rico.amslinger@informatik.uni-augsburg.de", "time": "Tue Feb 13 15:34:43 2018 +0100" }, "committer": { "name": "Rico Amslinger", "email": "rico.amslinger@informatik.uni-augsburg.de", "time": "Wed Feb 14 09:52:38 2018 +0000" }, "message": "mem, sim-se: Fixed seg-fault in EmulationPageTable::remap\n\nWhen moving a memory region the target region should be unmapped.\nThe assertion does reflect this, but the following line accesses\nthe invalid pointer regardless. This commit replaces the pointer\naccess with an emplace.\n\nChange-Id: I85f9be4e6c223eab447c75043e593ed3f90017e1\nReviewed-on: https://gem5-review.googlesource.com/8261\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-by: Brandon Potter \u003cBrandon.Potter@amd.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "4e13495f5d8e1e98609fd67b9b29c67eaeb753fc", "tree": "33219dcbe9e200b1a3242c06586387dfb315494c", "parents": [ "2d6afc6e2621fe67df09d4824ccd678a503b3517" ], "author": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Thu Feb 08 20:14:12 2018 +0000" }, "committer": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Tue Feb 13 18:22:29 2018 +0000" }, "message": "dev: Remove unused interrupt controller in Terminal\n\nChange-Id: I412d0b5edf2a08217792fa2ed1e511c17d3d31d4\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8141\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "2d6afc6e2621fe67df09d4824ccd678a503b3517", "tree": "c714bc1bc2af3b25b266849c515855b36f1e334e", "parents": [ "e9f736738d61775cd3b739dbc9f85cbf4f4c135f" ], "author": { "name": "Rekai Gonzalez-Alberquilla", "email": "rekai.gonzalezalberquilla@arm.com", "time": "Fri Feb 10 17:27:33 2017 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Feb 13 16:47:44 2018 +0000" }, "message": "sim: Make Stats truly non-copy-constructible\n\nThe stats are silently non-copy constructible. Therefore, when someone\ncopy-constructs any object with stats, asserts happen when registering\nthe stats, as they were not constructed in the intended way.\n\nThis patch solves that by explicitly deleting the copy constructor,\ntrading an obscure run-time assert for a compile-time somehow more\nmeaningful error meassage.\n\nThis triggers some compilation errors as the FaultStats in the fault\ndefinitions of ARM and SPARC use brace-enclosed initialisations in which\none of the elements derives from DataWrap, which is not\ncopy-constructible anymore. To fix that, this patch also adds a\nconstructor for the FaultVals in both ISAs.\n\nChange-Id: I340e203b9386609b32c66e3b8918a015afe415a4\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-by: Sascha Bischoff \u003csascha.bischoff@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8082\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "e9f736738d61775cd3b739dbc9f85cbf4f4c135f", "tree": "b30ab13dcc55d931ced19732e6ff9780bb1d42de", "parents": [ "6af3a7df1f42fe2ff1cb32ed5d373ce39691281f" ], "author": { "name": "Wendy Elsasser", "email": "wendy.elsasser@arm.com", "time": "Fri Feb 09 12:34:40 2018 -0600" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Fri Feb 09 21:17:31 2018 +0000" }, "message": "Fix DDR4_2400_8x8 DRAMCTRL configuration\n\nChange-Id: I7af361e146909acc158590354ab22732d4b2f3d5\nSigned-off-by: Wendy Elsasser \u003cwendy.elsasser@arm.com\u003e\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8101\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "6af3a7df1f42fe2ff1cb32ed5d373ce39691281f", "tree": "223a4801cb13a24b9e393baf202d2ccb27b72834", "parents": [ "3feeb994ae613fd6b3734c1a991285b2ecbd1946" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Mon Feb 05 17:08:43 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Feb 09 15:09:00 2018 +0000" }, "message": "sim: Remove _numContexts member in System class\n\nA System object has a _numContexts member variable which represent the\nnumber of ThreadContext registered in the System. Since this has to\nmatch the size of the ThreadContext vector, this patch removes the\nmanually cached size. This was usually used as a for-loop index, whereas\nwe want to enforce the use of range-based loops whenever possible.\n\nChange-Id: I1ba317c0393bcc9c1aeebbb1fc22d7b2bc2cf90c\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8062\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Brandon Potter \u003cBrandon.Potter@amd.com\u003e\n" }, { "commit": "3feeb994ae613fd6b3734c1a991285b2ecbd1946", "tree": "55e90a35ca28a2502cc0a01354425c240555562a", "parents": [ "5a3b9ca5833815641c355833040197614f8b147d" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Wed Jan 10 10:19:19 2018 -0800" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Fri Feb 09 00:52:09 2018 +0000" }, "message": "dev: Fix i8042 device errors\n\nThe patch that added M5_FALLTHROUGH (5c41076bd7610 misc: Updates for gcc7.2\nfor x86) incorrectly added breaks to the i8042 device without implementing\nthe correct functions. This patch implements keyboard writes, but ignores\noutput writes.\n\nInformation on the PS2 controller can be found at\nhttps://wiki.osdev.org/%228042%22_PS/2_Controller\n\nNote: Without this patch Linux 4.14 won\u0027t boot.\n\nChange-Id: I7de137b46cef00e6c1f1c14335cb52107cd7fe5b\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7301\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "5a3b9ca5833815641c355833040197614f8b147d", "tree": "30628f1ba5329add10c37503f05aef1746d7ffed", "parents": [ "718b53dc441abb80a8ba40d2ae22b40fd1c83427" ], "author": { "name": "Daniel R. Carvalho", "email": "odanrc@yahoo.com.br", "time": "Wed Feb 07 14:49:55 2018 +0100" }, "committer": { "name": "Daniel Carvalho", "email": "mr.danrc@gmail.com", "time": "Thu Feb 08 13:43:53 2018 +0000" }, "message": "mem-cache: Make cache warmup percentage a parameter.\n\nThe warmupPercentage is the percentage of different tags (based on the\ncache size) that need to be touched in order to warm up the cache.\nIf Warmup failed (i.e., not enough tags were touched), warmup_cycle \u003d 0.\n\nThe warmup is not being taken into account to calculate the stats (i.e.,\nstats acquisition starts before cache is warmed up). Maybe in the future\nthis functionality should be added.\n\nChange-Id: I2b93a99c19fddb99a4c60e6d4293fa355744d05e\nReviewed-on: https://gem5-review.googlesource.com/8061\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "718b53dc441abb80a8ba40d2ae22b40fd1c83427", "tree": "89ead18b8aecd4746939ce649be868c8171d96c0", "parents": [ "73b1160bd808cc523f49db37df597e4b2f3b9877" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Nov 28 16:00:02 2017 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Feb 08 10:53:18 2018 +0000" }, "message": "arch-arm: Correct SecureMonitorTrap vals for aarch32\n\nThis patch replaces the dummy values which were defined for the\nSecureMonitorTrap thus enabling its usage in aarch32 mode. 1) It\nchanges the vector table offset from 0x14 to 0x4 in compliance with the\narmv8 documentation. 2) When trapping in monitor mode for aarch32, the\nmon_lr is updated with the pc + a non zero offset (+4/2 depending on the\ncurrent instruction set: +4 for A32, +2 for T32).\n\nChange-Id: I01e1e52bf5ecd405e7472e31e01cf9a599153b08\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8041\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "73b1160bd808cc523f49db37df597e4b2f3b9877", "tree": "8a5494ac4611e67ff2efda4b008a3cbba5415916", "parents": [ "ad36e61ce400deaddfb07e71b13aea8a74b52550" ], "author": { "name": "Chuan Zhu", "email": "chuan.zhu@arm.com", "time": "Fri Jan 05 10:26:37 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Feb 08 10:24:56 2018 +0000" }, "message": "arch-arm: Fixed error in choosing vector offset\n\nThe old code chose vector offset associated with exceptions taken\nto EL3 by incorrectly using \"from64\", which is associated with the\nexception level where the exception was taken from. However, the\noffset should depends on the ISA of the lower EL and not of the\nstarting EL itself, as specified in ARM ARM. This patch corrects\nthis by implementing the method in AArch64.TakeException in ARM ARM.\n\nChange-Id: I8f7c9aa777c5f2eef9e2d89c36e9daee23f3a822\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8001\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "ad36e61ce400deaddfb07e71b13aea8a74b52550", "tree": "5268efd73e5369b1f98bdf492125424199bc1922", "parents": [ "b885dc68a26e0c7a401ca4b338d997ac577847a8" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Dec 19 10:18:13 2017 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Feb 08 09:48:02 2018 +0000" }, "message": "arch-arm: Don\u0027t change PSTATE in Illegal Exception return\n\nThis patch fixes the Illegal Exception return handler. According to the\narmarm documentation, when PSTATE.IL is set to one because of an illegal\nexception return, PSTATE.{EL, nRW, SP} are unchanged. This means the\nException level, Execution state, and stack pointer selection do not\nchange as a result of the return.\n\nChange-Id: I35f2fe68fb2822a54fc4a21930871eab7a1aaab4\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/8021\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "b885dc68a26e0c7a401ca4b338d997ac577847a8", "tree": "6e7ec04faf2f3c928f5ad836ec834293a273df5c", "parents": [ "b05a197d4c1d1c255eb90a7da302149414ebb0cf" ], "author": { "name": "Chuan Zhu", "email": "chuan.zhu@arm.com", "time": "Mon Jan 15 16:14:11 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Feb 08 09:27:25 2018 +0000" }, "message": "arch-arm: Handle route to EL2 in Supervisor Trap\n\nSupervisor Trap is supposed to be able to handle exceptions routed\nto EL2, which is enabled by HCR_EL2.TGE. This fix adds routeToHyp()\nfunction to Supervisor Trap to handle this, similar to that in\nUndefinedFault, DataAbort, etc.\n\nChange-Id: I1fcf9f2d445ecbc13c8f6d3b7d599728b0250ab7\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7961\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "b05a197d4c1d1c255eb90a7da302149414ebb0cf", "tree": "39c9af82daf6445c9a035734f8c0808d56661c88", "parents": [ "30e94319ab78542425b949317557eecc43af02ce" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Dec 20 19:20:42 2017 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Feb 07 16:14:39 2018 +0000" }, "message": "arch-arm: Change the type of fault for dc ivac instructions\n\nChange-Id: I00f957a3bc4721a66db62b1257f10e9019a94608\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7829\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "30e94319ab78542425b949317557eecc43af02ce", "tree": "375786d52196abde17671e840c2551d9b5e83a9f", "parents": [ "f54e874d645a1ae66a4b5c963f9d6f42cf2ef2cb" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Dec 20 17:25:31 2017 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Feb 07 16:14:39 2018 +0000" }, "message": "arch-arm: Unify permission checks for dc * instructions\n\nChange-Id: Ib47f4134e3f0a580e5356d384a5d3b293c1af7be\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7828\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "f54e874d645a1ae66a4b5c963f9d6f42cf2ef2cb", "tree": "867f34196f91c846ef78735d12732e700cf49e7b", "parents": [ "c364f58da916a6a1cb66c3e0276e898d77e1021b" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Thu Jan 04 15:14:26 2018 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Feb 07 16:14:39 2018 +0000" }, "message": "arch-arm: Check cache maintenance insts for permission faults\n\nIn AArch32, data cache maintenance instructions that operate by VA do\nnot generate permission faults.\n\nIn AArch64, a data cache invalidate instruction can generate a\npermission fault when there are no write permissions to the specified\nVA. Data cache clean and data cache clean and invalidate instructions\ndo not generate permission faults.\n\nChecks for external aborts are also bypassed for data cache\nmaintenance instructions.\n\nChange-Id: Iea5bc665e4cf66d528e36b671535b66637c4b224\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7827\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "c364f58da916a6a1cb66c3e0276e898d77e1021b", "tree": "acb02a2876489805fa17db918f20ef5693f62b0a", "parents": [ "4d9811cc5fd36a972e340ad82b14ab0ccaeb5cfa" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Tue Dec 19 21:49:08 2017 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Feb 07 16:14:39 2018 +0000" }, "message": "arch-arm: Turn dc ivac to dc civac when some conditions are met\n\nThe Arm ARM defines that at EL1 a data cache invalidate instruction\nperforms a data cache clean and invalidate operation if all of the\nfollowing apply:\n* EL2 is implemented,\n* HCR_EL2.VM is set to 1,\n* SCR_EL3.NS is set to 1 or EL3 is not implemented.\nThis changeset implements this behavior.\n\nChange-Id: I6b6aef2f4b1e7eb107c069fdb0a10f4aa8e6b196\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7826\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "4d9811cc5fd36a972e340ad82b14ab0ccaeb5cfa", "tree": "987d4e9038f71deab52cf814fd0f303609835201", "parents": [ "760e2eb6f4e40080a49e6372284c5213bf95475a" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Dec 20 12:13:08 2017 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Feb 07 16:14:39 2018 +0000" }, "message": "arch-arm: Fix printing of the data cache maintenance instructions\n\nChange-Id: I2322c7bf65b38cb07a1ea2b5dc25dfc5a0496cf0\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7825\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "760e2eb6f4e40080a49e6372284c5213bf95475a", "tree": "ea44514200a121ce3e653ca635adbd5e514a7fec", "parents": [ "f4e27c3ff56894e738bd2a975646b5a07d9ea75c" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Tue Dec 19 21:43:51 2017 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Feb 07 16:14:39 2018 +0000" }, "message": "arch-arm: Fix cache line size for cache maintenace inst\n\nCache maintenance operations operate on whole cache blocks. This\nchangeset uses the system cache line size as the size of the cache\nmaintenance requests and masks the lower bits of the effective\naddress.\n\nChange-Id: I6e7aefff51670c8cac39e4e73db21a0c5a0b7aef\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7824\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "f4e27c3ff56894e738bd2a975646b5a07d9ea75c", "tree": "7ed54c037502d2b97fb4a6eaaca46be18468f0f2", "parents": [ "b72d69c5caa382902fc200086e861e92ef883163" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Tue Dec 19 16:58:33 2017 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Feb 07 16:14:39 2018 +0000" }, "message": "arch-arm: Fault when dc ivac is executed from EL0\n\nA previous change enabled execution of dc ivac from EL0 when\nSCTLR_EL1.UCI\u003d1. The Arm ARM specifies that dc ivac is the only data\ncache maintenance operation by VA that cannot be executed from\nEL0. This changeset essential reverts the change:\n8d43922 arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI\u003d1\n\nChange-Id: Ia25fab13846a151f548e649a16067feb1ff65c9c\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7823\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "b72d69c5caa382902fc200086e861e92ef883163", "tree": "5e9d5761f066fb03be2171909de3cdd3d0faa7a8", "parents": [ "a1fc8b7ecdbadc3e9116594ed0803d2ed2612670" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Tue Dec 19 14:44:11 2017 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Feb 07 16:11:40 2018 +0000" }, "message": "mem-cache: Only pendingModified MSHRs can satisfy CMO snoops\n\nWe set the satisfied flag when a cache clean request encounters:\n1) a block with the dirty bit set, or\n2) a pending modified MSHR which means that the cache will get copy of\nthe block that will be soon modified.\n\nThis changeset fixes a previous bug that set the satisfied flag on\nsnooping MSHR hits even the pendingModified flags was not set.\n\nChange-Id: I4968c4820997be5cc1238148eea12a1ba39837d4\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Sudhanshu Jha \u003csudhanshu.jha@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7822\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "a1fc8b7ecdbadc3e9116594ed0803d2ed2612670", "tree": "64512c48e41b70270040c26ad492b707aca1b084", "parents": [ "7798ffb6948d12c7f2bc63dc9a3263bb19aa3297" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Thu Dec 14 17:36:09 2017 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Feb 07 16:11:31 2018 +0000" }, "message": "mem-cache: Cleaned blocks should be marked as not writable\n\nA writeclean packet writes a dirty block to the memory below and\ntherefore sets the dirty flag for the block when the memory below is a\ncache. If the block was also marked as writable it can satisfy future\nwrite requests without further requests/snoops. This can lead to\nmultiple copies of the same block marked as dirty which is not\nallowed. This changeset clears the writable flag from the cleaned\nblock to prevent the cache from satisfying future write requests\nwithout sending a downstream request.\n\nChange-Id: I14d3c62fd33f81b1a8ba62374c8565ccab00a6fe\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7821\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "7798ffb6948d12c7f2bc63dc9a3263bb19aa3297", "tree": "24e2a42dc06b980a86e7763b6b01d9fd7aa372e0", "parents": [ "633fdd5841d8e7798e1b1158261612a6ad84c812" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Jan 09 10:10:04 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Feb 07 15:13:49 2018 +0000" }, "message": "arch-arm: Change function name for banked miscregs\n\nThis commit changes the function\u0027s name used for retrieving the index of a\nsecurity banked register given the flatten index. This will avoid confusion\nwith flattenRegId, which has a different purpose.\n\nChange-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7982\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "633fdd5841d8e7798e1b1158261612a6ad84c812", "tree": "a572e3d8be8e82d2be24e3d1d6da54818e3e4f41", "parents": [ "78024e6b026fecc780e503aa246beeb10dcc26d9" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Dec 14 17:38:38 2017 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Feb 07 15:13:49 2018 +0000" }, "message": "arch-arm: Fix AArch32 SETEND Instruction\n\nThis patch fixes AArch32 SETEND instruction, which was previously\nexecuted unconditionally without checking (H)SCTLR.SED field. This bit\nenables/disables the trapping of the instruction.\n\nChange-Id: Ib3d2194c8d16c34ec2a9ab3e8090081900c1e42e\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7981\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "78024e6b026fecc780e503aa246beeb10dcc26d9", "tree": "297b14853c7b0fa0b8c59c0f475ff1aaa908a519", "parents": [ "465705e18087a22caec9cacc2c538a86014aff19" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Jan 03 11:02:00 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Feb 07 15:06:50 2018 +0000" }, "message": "arch-arm: Correct Illegal Exception Return detection\n\nFixed Illegal Exception Return detection, which was not\ncovering all the documented cases.\n\nChange-Id: If08ddc1490d1c0a1fccee1489d116384770ce0a5\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7223\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "465705e18087a22caec9cacc2c538a86014aff19", "tree": "bc8616b6f6680cf8a8f48afc244faeb4740508ce", "parents": [ "d7062b1273dfcfac0690dff88470c4ebf28f09c1" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Jan 03 11:01:17 2018 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Feb 07 15:06:50 2018 +0000" }, "message": "arch-arm: ELUsingAArch32K from armarm pseudocode\n\nThis patch implements the ELUsingAArch32K pseudocode, which is returning\ntrue if the provided Exception Level is using A32 ISA, but it is not\npanicking (quitting simulation) if the information is unknown (see\ndocumentation).\nThe panicking is the current behaviour of the ELIs32 utility in gem5.\n\nChange-Id: Iad7b56077d7e0f8ee223b5b9593cb8097f26bb29\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7222\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "d7062b1273dfcfac0690dff88470c4ebf28f09c1", "tree": "fc6bd9d0a1a72176caa9482b957f06b60f994f29", "parents": [ "234fba56bc6dde84c9a6a57e539676fa55b0ff76" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Dec 22 12:30:05 2017 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Feb 07 15:06:50 2018 +0000" }, "message": "arch-arm: isSecureBelow from armarm pseudocode\n\nThis patch introduces the inSecureBelow pseudocode function\ndefined in the armarm documentation. It also replaces the\ninSecureState function call which was improperly used in\nELIs32: we might be in secure state (EL3), but with non-secure\nlower ELs (SCR.NS \u003d 1).\n\nChange-Id: I01febcb54392ad4e51e785b4d5153aeb3437c778\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Chuan Zhu \u003cchuan.zhu@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7221\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "234fba56bc6dde84c9a6a57e539676fa55b0ff76", "tree": "cd5c3a36c1f123d5d45f179af86981b736823d5c", "parents": [ "0f2e20c80aa6bbc87f3791a8fdf81489ad501a40" ], "author": { "name": "Chuan Zhu", "email": "chuan.zhu@arm.com", "time": "Wed Jul 26 17:40:36 2017 +0100" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Feb 07 15:06:50 2018 +0000" }, "message": "arch-arm: Fix incorrect assumptions in ELIs64\n\nThe state of EL1 wasn\u0027t determined correctly when running in secure\nmode if virtualisation was enabled. This changset updates the\nimplementation to match the canonical behavior from the ARM ARM.\n\nChange-Id: I7ed6f5c003617773603f678667aac069d73b6f62\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7141\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "0f2e20c80aa6bbc87f3791a8fdf81489ad501a40", "tree": "5364ae00339d69c72544e38973eeb0d735736e59", "parents": [ "ecee328c9244504f616a3b8cd352fca3d3e4b6e7" ], "author": { "name": "Daniel R. Carvalho", "email": "odanrc@yahoo.com.br", "time": "Tue Feb 06 11:24:30 2018 +0100" }, "committer": { "name": "Daniel Carvalho", "email": "mr.danrc@gmail.com", "time": "Tue Feb 06 16:13:27 2018 +0000" }, "message": "mem-cache: Remove extra numSets zero check.\n\nnumSets is unsigned, so it cannot be lower than 0. Besides, isPowerOf2(0)\nis false by definition (and implemmentation*), so there is no need for the\ndouble check.\n\n* As presented in base/intmath.hh\n\nChange-Id: I3f6296694a937434feddc7ed21f11c2a6fdfc5a9\nReviewed-on: https://gem5-review.googlesource.com/7901\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "ecee328c9244504f616a3b8cd352fca3d3e4b6e7", "tree": "4a551953d452215f091491226c2c78d74d085401", "parents": [ "d5b9ffda458c0e1b7ad52b42d7c8caf2b4a5c022" ], "author": { "name": "Daniel R. Carvalho", "email": "odanrc@yahoo.com.br", "time": "Mon Feb 05 16:32:23 2018 +0100" }, "committer": { "name": "Daniel Carvalho", "email": "mr.danrc@gmail.com", "time": "Tue Feb 06 10:26:27 2018 +0000" }, "message": "mem: Standardize mem folder header guards\n\nStandardize all header guards in the mem directory according to the most\nfrequent patterns. In general they have the form:\n mem: __FOLDER_TREE_FILE_NAME_HH__\n ruby: __FOLDER_TREE_FILENAME_HH__\n\nChange-Id: I983853e292deb302becf151bf0e970057dc24774\nReviewed-on: https://gem5-review.googlesource.com/7881\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "d5b9ffda458c0e1b7ad52b42d7c8caf2b4a5c022", "tree": "5d3b7364d285c1990aa42278c63a30545f366f3b", "parents": [ "5f9795a4e0b4dd7dd7ec758ab8c58a4b423856db" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sat Feb 03 22:25:14 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Feb 05 22:16:54 2018 +0000" }, "message": "base: Update #includes for bitunion.hh.\n\n\u003ciostream\u003e isn\u0027t actually used anywhere in bitunion.hh. The templated\nhash struct type is defined in \u003cfunctional\u003e and should be included\nexplicitly.\n\nChange-Id: I8691ccb2f9e28a01610ae8bb4d9591b07cb7320b\nReviewed-on: https://gem5-review.googlesource.com/7781\nReviewed-by: Matthias Jung \u003cjungma@eit.uni-kl.de\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "5f9795a4e0b4dd7dd7ec758ab8c58a4b423856db", "tree": "6eaebc71f74548a01f3f0ea56d799914dffbfe45", "parents": [ "0c208d94cac1f89a04a5adb242327fa9fd13d70e" ], "author": { "name": "Nayan Deshmukh", "email": "nayan26deshmukh@gmail.com", "time": "Sun Feb 04 17:58:46 2018 +0530" }, "committer": { "name": "Nayan Deshmukh", "email": "nayan26deshmukh@gmail.com", "time": "Mon Feb 05 17:36:55 2018 +0000" }, "message": "config: remove dead code in fs.py\n\nWe have not added the --generate-dtb option for non-ARM systems and\nhence this case becomes dead code. It also leads to error on non-ARM\nsystems as is tries to access a non existent field.\n\nChange-Id: Ia926bd0c61efa275bc5e3864b8a9c3ffb7aa3cb5\nSigned-off-by: Nayan Deshmukh \u003cnayan26deshmukh@gmail.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7801\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "0c208d94cac1f89a04a5adb242327fa9fd13d70e", "tree": "bd6ac77f925cd6348440aa5bdc3c235c91df2de6", "parents": [ "eea11aedcfe18b29d6e63243bc1acb51441ef523" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Nov 08 11:24:58 2017 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Mon Feb 05 09:44:22 2018 +0000" }, "message": "cpu: MinorCPU handling IsSquashAfter flag\n\nMinorCPU was not handling IsSquashAfter flagged instructions. The\nbehaviour was to force a branch (hence enforcing refetching) for\nSerializeAfter instructions only. This has now been extended to\nSquashAfter in order to correctly support ISB barrier instruction\nbehaviour.\n\nChange-Id: Ie525b23350b0de121372d3b98b433e36b097d5c4\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/5702\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "eea11aedcfe18b29d6e63243bc1acb51441ef523", "tree": "a8da293007189f6217164adfccb3157f57679fad", "parents": [ "4910d36e765875b6531b13c2a98f958082cc3de0" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Mon Nov 06 15:22:43 2017 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Mon Feb 05 09:44:22 2018 +0000" }, "message": "arch-arm: Removing Serializing flag from ISB\n\nISB Serializing behaviour is guaranteed by IsSquashAfter,\nwhich is inherently serializing; when instruction is commited,\nconsecutive instructions are flushed and refetched.\n\nChange-Id: I05e61b4cf9f01113d95b1502c996d04cbd69b759\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/5701\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "4910d36e765875b6531b13c2a98f958082cc3de0", "tree": "98f0db527611dac3838d1bf2f34ee80872ce93a6", "parents": [ "257a67826291712202299957223c64af7a61ea98" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Thu Feb 01 17:57:48 2018 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Fri Feb 02 17:43:30 2018 +0000" }, "message": "base: Fix unused function warning\n\nAfter refactoring the remote gdb interface, break_type is declared as\nconst function and is only used as a parameter to DPRINTF function\ncalls. This means that it is seen as unused when compiling\ngem5.fast. This changeset fixes the warning.\n\nChange-Id: Iea89b66c53c62341c043d8bd3838ebc27ee333bc\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/7741\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "257a67826291712202299957223c64af7a61ea98", "tree": "5e57dd2fc3660ec73be57902b11b1581159e67b7", "parents": [ "c872143864dcfee85c22db3904b4c05d0f1ddeae" ], "author": { "name": "Sujay Phadke", "email": "electronicsguy123@gmail.com", "time": "Tue Jan 23 23:24:12 2018 +0530" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Feb 01 04:43:48 2018 +0000" }, "message": "alpha: fix for no \u0027break\u0027 in the case statement\n\ngem5 won\u0027t compile correctly since g++ will throw a warning (error)\nthat the next case statement below this one is reachable since there is\nno \u0027break\u0027 statement.\n\nSigned-off-by: Sujay Phadke\n\nChange-Id: Icab646ee5abcfeb6ba3e690909042927b4003eba\nReviewed-on: https://gem5-review.googlesource.com/7521\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Brandon Potter \u003cBrandon.Potter@amd.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "c872143864dcfee85c22db3904b4c05d0f1ddeae", "tree": "9b0d4d76bd298fe774b673da12693f924cd81737", "parents": [ "b919065ac9144ad1280851c1050a4136854423d6" ], "author": { "name": "Hanhwi Jang", "email": "jang.hanhwi@gmail.com", "time": "Tue Jan 30 19:17:33 2018 +0900" }, "committer": { "name": "Hanhwi Jang", "email": "jang.hanhwi@gmail.com", "time": "Thu Feb 01 03:45:16 2018 +0000" }, "message": "scons: Resolve backtrace implementation existence testing failure\n\nChange backtrace implementation testing code not to have NULL pointer.\n\nSCons fails to find backtrace implementation even if it exists.\nThe implementation testing code contains NULL pointers as a backtrace\nbuffer argument. Some compilers check the buffer is NULL pointed\nor not, and generate a compilation error.\n\nChange-Id: Icc5bc9a887b7a6bbc804b5b8a5a35a935c78a922\nReviewed-on: https://gem5-review.googlesource.com/7681\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "b919065ac9144ad1280851c1050a4136854423d6", "tree": "460fff2fc2485bb92257c7075be6ee02bf3ebea4", "parents": [ "3e52d9fb3328258139f3523175d28ae8f11af702" ], "author": { "name": "Christian Menard", "email": "christian.menard@tu-dresden.de", "time": "Tue Jan 30 11:12:31 2018 +0100" }, "committer": { "name": "Christian Menard", "email": "christian.menard@tu-dresden.de", "time": "Wed Jan 31 10:11:51 2018 +0000" }, "message": "arch-x86: consistent style of comments in system files\n\nChange-Id: I9f208819b8c1a5c46a77262eb533bb47adb2b905\nReviewed-on: https://gem5-review.googlesource.com/7701\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-by: Brandon Potter \u003cBrandon.Potter@amd.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "3e52d9fb3328258139f3523175d28ae8f11af702", "tree": "41340b7487e2aae28167a68cd0e1b9a44b43e3fb", "parents": [ "89f2871168bcd2a69f3edc2e9f12f3bc66101128" ], "author": { "name": "Maximilian Stein", "email": "maximilian.stein@tu-dresden.de", "time": "Mon Jan 29 12:21:32 2018 +0100" }, "committer": { "name": "Christian Menard", "email": "christian.menard@tu-dresden.de", "time": "Tue Jan 30 09:52:13 2018 +0000" }, "message": "arch-x86: Granularity bit and segment limit\n\nIf set, the granularity bit indicates that the segment limit of segment\ndescriptors shall be interpreted as number of 4K blocks rather than\nbytes.\n\nThe high part (bit 48 to 51) of segment descriptor limits is only 4 bits\nwide while the low part (bit 0 to 15) spans 16 bits.\n\nChange-Id: Ie386224ca815275fdb31498fe68310ed9c62cc87\nReviewed-on: https://gem5-review.googlesource.com/7601\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "89f2871168bcd2a69f3edc2e9f12f3bc66101128", "tree": "fe9d4e09989b87e978afc345f217184209a57e93", "parents": [ "cca6459b4fe68593137cb0f3ede7d1415cdbd522" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Jan 29 15:17:08 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Jan 29 23:49:36 2018 +0000" }, "message": "riscv: Add overrides to various StaticInst methods.\n\nThis makes riscv compile with the version of clang(++) I have on my\nworkstation.\n\nChange-Id: I0478616810fbc8a715fd61323b7e0f73676c8328\nReviewed-on: https://gem5-review.googlesource.com/7643\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "cca6459b4fe68593137cb0f3ede7d1415cdbd522", "tree": "0afa5d9b94e28a8bb805f26b21ccf2d7c80567de", "parents": [ "ba7a202ffac695dd2c6c9c7254d34d89dea68eaf" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Jan 29 14:42:26 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Jan 29 23:48:24 2018 +0000" }, "message": "base: Remove the ability to cprintf stringstreams directly.\n\nThe cprintf functions don\u0027t know ahead of time what format characters\nare going to be used with what underlying data types, and so any\ntype must be minimally usable with the default specialization of\nformat_integer, format_char, format_float and format_string. All of\nthose functions ultimately print their parameter with out \u003c\u003c data\nexcept the one which prints stringstreams. That function accesses the\nbuffer of the string stream with .str(), and then prints that instead.\n\nThat should technically work out ok as long as stringstreams are only\nprinted using %s, but there\u0027s no way to guarantee that ahead of time.\nTo avoid that problem, and because gem5 doesn\u0027t ever actually use the\nability to print stringstreams directly, this change removes that\nfeature and modifies the corresponding part of the unit test.\n\nIf we ever do want to print the contents of a string stream, it won\u0027t\nbe difficult to add a .str() to it.\n\nChange-Id: Id902eaff042b96b374efe0183e5e3be9626e8c88\nReviewed-on: https://gem5-review.googlesource.com/7642\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "ba7a202ffac695dd2c6c9c7254d34d89dea68eaf", "tree": "9733f7cfd228bc70a77a76d3a48841570da81ec6", "parents": [ "9d04c02c51550c3654126f5e658bce623ba384d6" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Jan 29 14:38:37 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Jan 29 23:47:55 2018 +0000" }, "message": "base: Delete commented out versions of the format_integer function.\n\nIf they\u0027re needed, they\u0027d be fairly easy to recreate and are also\navailable in the revision history.\n\nChange-Id: I5cf5e4b1271ce488016464048de69bc643dee4d9\nReviewed-on: https://gem5-review.googlesource.com/7641\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "9d04c02c51550c3654126f5e658bce623ba384d6", "tree": "7dafcda92ca96af5ca880ac7e3a396eb9cbb065d", "parents": [ "c1513c69cad2c26c6dcb66416e152952ceb0597e" ], "author": { "name": "Curtis Dunham", "email": "Curtis.Dunham@arm.com", "time": "Wed Dec 06 16:51:26 2017 -0600" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:31:36 2018 +0000" }, "message": "arch-arm: understandably initialize register permissions\n\nMove massive initialization routine to the bottom of miscregs.cc.\nAdditionally, share register metadata across ISA instances by\nmaking lookUpMiscReg a static member of the ISA and only\ninitializing it once.\n\nChange-Id: I6d6ab26200c4e781151cc6efd97ce2420e2bf4cc\nSigned-off-by: Curtis Dunham \u003cCurtis.Dunham@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/6803\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "c1513c69cad2c26c6dcb66416e152952ceb0597e", "tree": "942112a2cdaf5901504288afce5cf0ed7a3300f7", "parents": [ "04251da6a92fa7b0779d58e194fb1bfa84b3514e" ], "author": { "name": "Curtis Dunham", "email": "Curtis.Dunham@arm.com", "time": "Fri Nov 03 17:39:45 2017 -0500" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:31:20 2018 +0000" }, "message": "arm: extend MiscReg metadata structures\n\nImplement proper handling of RES0/RES1 and RAZ/RAO bitfields.\n\nChange-Id: I344c32c3fb1d142acfb0521ba3590ddd2b1f5360\nSigned-off-by: Curtis Dunham \u003cCurtis.Dunham@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/6802\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "04251da6a92fa7b0779d58e194fb1bfa84b3514e", "tree": "085a78ea187c2a249f3dbde420be217eb822058f", "parents": [ "30919a7ef5b8d36069139e928f3b188122c50572" ], "author": { "name": "Curtis Dunham", "email": "Curtis.Dunham@arm.com", "time": "Wed Dec 06 14:42:07 2017 -0600" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:30:56 2018 +0000" }, "message": "arch-arm: understandably initialize register mappings\n\nThe mappings for sharing a backing store between AArch32\nand AArch64 system registers are made clearer using an\ninitializer object.\n\nChange-Id: I29dcfab2797b4d36b3182342997edffde334a291\nSigned-off-by: Curtis Dunham \u003cCurtis.Dunham@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jack Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/6801\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "30919a7ef5b8d36069139e928f3b188122c50572", "tree": "ae4f679844537002b067bc27c0c8958c2e25ce12", "parents": [ "dcab5b577e35f9bf9969ccfd91309455758aaed8" ], "author": { "name": "Curtis Dunham", "email": "Curtis.Dunham@arm.com", "time": "Mon Sep 11 15:17:00 2017 -0500" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:22:56 2018 +0000" }, "message": "config, arm: enable device tree autogeneration for bigLITTLE\n\nChange-Id: Iaa5eeb3504b3ff9e46b6f592a06d6b833c830d83\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/5969\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "dcab5b577e35f9bf9969ccfd91309455758aaed8", "tree": "2ef530467a6d67caa152af3572b309f41146b67e", "parents": [ "7c9122b6f2365bae51903f125ccaa9c4b779ea26" ], "author": { "name": "Glenn Bergmans", "email": "glenn.bergmans@arm.com", "time": "Mon Mar 14 20:29:12 2016 +0000" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:22:51 2018 +0000" }, "message": "config: Embed Device Tree generation in fs.py config\n\nEquips the fs.py config routine with an extra commandline option\n--generate-dtb that will generate a dtb file automatically before\nrunning the simulation. Only works with ARM systems and gives a warning\nif the simulated system is not of --machine-type VExpress_GEM5_V1.\n\nChange-Id: I7766e5459fd9bec2245de83cef103091ebaf7229\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/5968\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "7c9122b6f2365bae51903f125ccaa9c4b779ea26", "tree": "8bbb3c02645e4587702e866978f3b6eec1e97613", "parents": [ "aa80cc9edbfb46b1a83342a32858c1cf48ac61a2" ], "author": { "name": "Glenn Bergmans", "email": "glenn.bergmans@arm.com", "time": "Fri Jan 22 15:40:14 2016 +0000" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:22:41 2018 +0000" }, "message": "arm: DT autogeneration - generate PCI node\n\nEnables automatic generation of Device Trees for RealView PCI host\ncontrollers. Note that some parts are more hard coded than you\u0027d want,\nbut this is due to the limited understanding the PCI host has of its\nconfiguration (i.e. it doesn\u0027t know all memory ranges). Fixing this,\nfor now at least, went beyond the scope and intentions of the\nDevice Tree generating code: use with care!\n\nChange-Id: I2041871e0eb4d04fb5191257c47dd38649d1c0cc\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/5967\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "aa80cc9edbfb46b1a83342a32858c1cf48ac61a2", "tree": "6926eda814931f154982fbb67ca8600d859ee7ca", "parents": [ "199ff5e67770592ee9cbb941db8e8ea740dc1084" ], "author": { "name": "Glenn Bergmans", "email": "glenn.bergmans@arm.com", "time": "Fri Jan 22 15:40:14 2016 +0000" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:22:29 2018 +0000" }, "message": "arm: DT autogeneration - Generate energy controller node\n\nAdds Device Tree methods for the energy controller to allow for\nDVFS simulations with automatically generated DTB files\n\nChange-Id: Id8682f07dff1bbe63987e757faa0694e03ee86ab\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/5966\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "199ff5e67770592ee9cbb941db8e8ea740dc1084", "tree": "59151aaee4f78a8f275fc5eeb830878beb29afde", "parents": [ "1a51f335ffbcf9abb685ae18daa8d00aecc6bee8" ], "author": { "name": "Glenn Bergmans", "email": "glenn.bergmans@arm.com", "time": "Thu Dec 17 11:49:51 2015 +0000" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:22:23 2018 +0000" }, "message": "arm: DT autogeneration - autogenerate RealView Platform devices\n\nImplements the Device Tree generating code for devices required by the\nRealView VExpress_GEM5_V1 platform\n\nChange-Id: I14244b2f3c028cbddba3c23ce7433fe3b301a0e8\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/5965\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "1a51f335ffbcf9abb685ae18daa8d00aecc6bee8", "tree": "0c631173f16ab60ec4f1bd098578485ff81e4b80", "parents": [ "7e9adcce565a00de9091d7d0f9b46d9e479e6625" ], "author": { "name": "Glenn Bergmans", "email": "glenn.bergmans@arm.com", "time": "Fri Jan 22 15:25:40 2016 +0000" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:22:06 2018 +0000" }, "message": "arm: DT autogeneration - Generate memory node\n\nImplements a high level method for generating a Device Tree node for\nan AbstractMemory object.\n\nChange-Id: I544ec642f182f103df26de535fdfaf03b3787a08\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/5964\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "7e9adcce565a00de9091d7d0f9b46d9e479e6625", "tree": "436fc9e05b30cd5e68d75b922daa902d0486b9e2", "parents": [ "7c8662f54a6beb4c07da4b2b58f19e5b94909bc8" ], "author": { "name": "Glenn Bergmans", "email": "glenn.bergmans@arm.com", "time": "Fri Jan 22 15:23:03 2016 +0000" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:21:48 2018 +0000" }, "message": "arm: DT autogeneration - Generate cpus node\n\nEquips cpu models with a method to generate the cpu node.\n\nNote: even though official documentation requires that CPU ids start\ncounting from 0 in every cluster, GEM5 requires a globally unique cpu_id.\n\nChange-Id: Ida3e17af3124a68ef7dbf2449cd034dfc3ec39df\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/5963\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "7c8662f54a6beb4c07da4b2b58f19e5b94909bc8", "tree": "9b7ff9b17903a6e795f6624c24739af81b3692d9", "parents": [ "3da05785813662f647b07400734337630a9f6f78" ], "author": { "name": "Glenn Bergmans", "email": "glenn.bergmans@arm.com", "time": "Wed Dec 16 15:43:42 2015 +0000" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:21:30 2018 +0000" }, "message": "arm: DT autogeneration - Device Tree generation methods\n\nThis patch adds an extra layer to the pyfdt library such that usage\ngets easier and device tree nodes can be specified in less code,\nwithout limiting original usage. Note to not import both the pyfdt\nand fdthelper in the same namespace (but generally fdthelper is all\nyou need, because it supplies the same classes even when they are not\nextended in any way)\n\nAlso, this patch lays out the primary functionality for generating a\ndevice tree, where every SimObject gets an empty generateDeviceTree\nmethod and ArmSystems loop over their children in an effort to merge\nall the nodes. Devices are implemented in other patches.\n\nChange-Id: I4d0a0666827287fe42e18447f19acab4dc80cc49\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/5962\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "3da05785813662f647b07400734337630a9f6f78", "tree": "10fc8a4b9265fc0b057e93f37d7f491c046c6f7d", "parents": [ "9f5b6e1b74c8289050836abdfb9c2539380f9105" ], "author": { "name": "Glenn Bergmans", "email": "glenn.bergmans@arm.com", "time": "Wed Dec 16 15:43:42 2015 +0000" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:20:06 2018 +0000" }, "message": "ext: DT autogeneration - Add PyFtd to m5 space\n\nThis patch adds pyfdt.py to the m5.ext module. This is used in\nsucceeding patches for generating and editing dtb files and flat\ndevice trees for DT autogeneration.\n\nThe file is in the m5_root/src/python/m5/ext directory, as opposed to\nthe m5_root/ext, because this library is part of the m5 object space\nand linking to the m5_root/ext directory from the SConscript file\nin src/python can not be done reliably. Linking from the root level\nSConscript is also not an option, because it doesn\u0027t have the PySource\nmethod defined.\n\nCloned from: https://github.com/superna9999/pyfdt\nCommit: accbcd254584c9295a18878d32999d0c7c156f8e\nVersion: 0.3\n\nChange-Id: I928bdc912a9507d1f8a3290acf445c7cae496552\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Curtis Dunham \u003ccurtis.dunham@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/5961\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "9f5b6e1b74c8289050836abdfb9c2539380f9105", "tree": "9b5dc7cdee74400580241907d8b50b3ed69a02ee", "parents": [ "624a026a393104e6730731695d5d74addd65d79e" ], "author": { "name": "Curtis Dunham", "email": "Curtis.Dunham@arm.com", "time": "Thu Sep 07 16:13:54 2017 -0500" }, "committer": { "name": "Curtis Dunham", "email": "curtis.dunham@arm.com", "time": "Mon Jan 29 22:19:55 2018 +0000" }, "message": "arm: make Arm GenericTimer a ClockedObject\n\nWithin a device tree, the GenericTimer device needs to point (via phandle)\nto a clock domain which is itself also an object in the device tree. Within\ngem5, clock domains are managed by making all clocked SimObjects inherit\nfrom ClockedObject rather than SimObject.\n\nWithout this change, the GenericTimer is unable to generate the appropriate\nclock domain phandle, and will crash during DTB autogeneration.\n\nChange-Id: I6d3fb6362847c6a01720b2f14b3d595d1e59f01f\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/4960\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "624a026a393104e6730731695d5d74addd65d79e", "tree": "23c9d49a100be452414e8b0a24f013ea2a5fca02", "parents": [ "66c37275ea3acb768d371c46c06a91d7052db8a8" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sat Jan 27 03:18:15 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sat Jan 27 20:29:06 2018 +0000" }, "message": "base: Add an \"override\" to name() in the HardBreakpoint class.\n\nclang reports an error otherwise and fails to compile.\n\nChange-Id: I3603d6c710641f1289e35c67f89a49f5cb71e95e\nReviewed-on: https://gem5-review.googlesource.com/7582\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "66c37275ea3acb768d371c46c06a91d7052db8a8", "tree": "bfb0b893f0e78591030f10e1aafee83b290bf332", "parents": [ "3ccef3dd7702530718f145c4c30061688ebe276f" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sat Jan 27 03:15:13 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sat Jan 27 20:28:40 2018 +0000" }, "message": "base: Get bitunions to compile on clang 3.8.\n\nclang was getting very upset and interpretting a member function\npointer as a call to the actual underlying function, and then\ncomplaining that it was a non-static function call without an instance.\n\nIt seems what it was really upset about was that the class who\u0027s scope\nthe member function pointer belonged to (the current class) wasn\u0027t done\nbeing defined. This *should* be ok as far as I can tell, but clang was\nhaving none of it.\n\nThis change reworks how the type of the setter function arguments are\ndetermined to work around that limitation. The bitunion test was run\nwith clang++ and g++ and both pass, and I\u0027ve built gem5.opt for ARM\nsuccessfully.\n\nChange-Id: Ib9351784a897af4867fe08045577e0247334ea11\nReviewed-on: https://gem5-review.googlesource.com/7581\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "3ccef3dd7702530718f145c4c30061688ebe276f", "tree": "2ca19a4ff18b9f27baff911bde45ee4ce633f305", "parents": [ "83f2b253989fd6dfc8f48d5368ae351ade91cfc6" ], "author": { "name": "Hanhwi Jang", "email": "jang.hanhwi@gmail.com", "time": "Sun Dec 10 02:02:34 2017 +0900" }, "committer": { "name": "Hanhwi Jang", "email": "jang.hanhwi@gmail.com", "time": "Thu Jan 25 12:11:24 2018 +0000" }, "message": "util: Implement Lua module for m5ops.\n\nThis module allows m5ops to be executed in Lua programs.\nTo compile it (in util/m5):\n The following command generates Lua moduel, gem5OpLua.so.\n\n make -f Makefile.\u003carch\u003e gem5OpLua.so\n\nTo use it:\n First, put gem5OpLua.so in Lua library search path.\n Then, import the module and execute the m5op function.\n\nExample usage, creating a checkpoint.\n\n m5 \u003d require(\"gem5OpLua\")\n m5.do_checkpoint(0, 0)\n\nChange-Id: Icc18a1fb6c050afeb1cf4558fbdc724fb26a90e2\nReviewed-on: https://gem5-review.googlesource.com/6541\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "83f2b253989fd6dfc8f48d5368ae351ade91cfc6", "tree": "c11f04427040c2efedb3cbfea8227293861ba8ff", "parents": [ "b074a15ec16b595cbe00cb63e2feff40059b60fb" ], "author": { "name": "Swapnil Haria", "email": "swapnilster@gmail.com", "time": "Mon Jan 15 21:49:17 2018 -0600" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Tue Jan 23 22:17:46 2018 +0000" }, "message": "arch-x86: Adding clflush, clflushopt, clwb instructions\n\nThis patch adds support for cache flushing instructions in x86.\nIt piggybacks on support for similar instructions in arm ISA\nadded by Nikos Nikoleris. I have tested each instruction using\nmicrobenchmarks.\n\nChange-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d\nReviewed-on: https://gem5-review.googlesource.com/7401\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "b074a15ec16b595cbe00cb63e2feff40059b60fb", "tree": "c9eb0c143b49d70dcf7a7a9d06229fc87b6a8147", "parents": [ "a4e722725c90677d555675eca616c9d0990393f1" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Jan 08 23:44:40 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Jan 23 20:39:24 2018 +0000" }, "message": "arch: Remove the \"arch/tlb.hh\" switching header.\n\nThis header is no longer used.\n\nChange-Id: I8da7f8618d647dd11c581818c13855c4e20d32d2\nReviewed-on: https://gem5-review.googlesource.com/7351\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "a4e722725c90677d555675eca616c9d0990393f1", "tree": "ed9a8268f73742fd4b4acbaf8e8434b67dc5fed7", "parents": [ "db8c55dede65e07cb9ea8e95c48badd2ea24462f" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Jan 08 23:37:57 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Jan 23 20:39:17 2018 +0000" }, "message": "tarch, mem: Abstract the data stored in the SE page tables.\n\nRather than store the actual TLB entry that corresponds to a mapping,\nwe can just store some abstracted information (address, a few flags)\nand then let the caller turn that into the appropriate entry. There\ncould potentially be some small amount of overhead from creating\nentries vs. storing them and just installing them, but it\u0027s likely\npretty minimal since that only happens on a TLB miss (ideally rare),\nand, if it is problematic, there could be some preallocated TLB\nentries which are just minimally filled in as necessary.\n\nThis has the nice effect of finally making the page tables ISA\nagnostic.\n\nChange-Id: I11e630f60682f0a0029b0683eb8ff0135fbd4317\nReviewed-on: https://gem5-review.googlesource.com/7350\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "db8c55dede65e07cb9ea8e95c48badd2ea24462f", "tree": "8b8b4fad738f3ecd3907bb6157517cc0e8a822eb", "parents": [ "8cb6bb444a6ee0106807d0a22bbc63323b410bf8" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Jan 08 04:41:25 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Jan 23 20:14:48 2018 +0000" }, "message": "x86, mem: Rewrite the multilevel page table class.\n\nThe new version extracts all the x86 specific aspects of the class,\nand builds the interface around a variable collection of template\narguments which are classes that represent the different levels of the\npage table. The multilevel page table class is now much more ISA\nindependent.\n\nChange-Id: Id42e168a78d0e70f80ab2438480cb6e00a3aa636\nReviewed-on: https://gem5-review.googlesource.com/7347\nReviewed-by: Brandon Potter \u003cBrandon.Potter@amd.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "8cb6bb444a6ee0106807d0a22bbc63323b410bf8", "tree": "2c0ec220b99ce9e764b0e551538f1622369db6c3", "parents": [ "2e5da9229547eeb3da02205e7c789c3ae589feff" ], "author": { "name": "Hanhwi Jang", "email": "jang.hanhwi@gmail.com", "time": "Wed Jan 10 11:39:38 2018 +0900" }, "committer": { "name": "Hanhwi Jang", "email": "jang.hanhwi@gmail.com", "time": "Sat Jan 20 09:07:44 2018 +0000" }, "message": "util: Implement PIC version of m5ops for X86.\n\nUsing m5ops for X86 in shared objects requires PIC for the m5ops.\nTypically, the PIC version is used to make m5op interfaces to other\nlanguages like python and lua.\n\nChange-Id: I2463904c13ea8b839d0386d3c743d8dad1e1e6bc\nReviewed-on: https://gem5-review.googlesource.com/7261\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "2e5da9229547eeb3da02205e7c789c3ae589feff", "tree": "c53885a5fac8422bc6bc86a9532ecbab4be8df85", "parents": [ "fd678694ee6bf9defe10d76e01c3e728a25d1871" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sun Jan 07 21:32:39 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sat Jan 20 08:08:39 2018 +0000" }, "message": "x86, mem: Don\u0027t try to force physical addresses on the system.\n\nUse the system object to allocate physical memory instead of manually\nplacing certain structures and then forcing the system to start other\nallocations after them in physical memory.\n\nChange-Id: Ie18c81645c3b648c64a6d7a649a0e50f7028f344\nReviewed-on: https://gem5-review.googlesource.com/7346\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-by: Brandon Potter \u003cBrandon.Potter@amd.com\u003e\n" }, { "commit": "fd678694ee6bf9defe10d76e01c3e728a25d1871", "tree": "fae5d677b57395bd48e85b0ab8c37726718f872f", "parents": [ "703662624ca9f6f5454b4d1ac773475c0af1bec5" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Jan 05 23:52:29 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sat Jan 20 08:08:06 2018 +0000" }, "message": "x86, mem: Get rid of PageTableOps::getBasePtr.\n\nPass this constant into the page table constructor.\n\nChange-Id: Icbf730f18d9dfcfebd10a196f7f799514728b0fb\nReviewed-on: https://gem5-review.googlesource.com/7345\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-by: Brandon Potter \u003cBrandon.Potter@amd.com\u003e\n" }, { "commit": "703662624ca9f6f5454b4d1ac773475c0af1bec5", "tree": "68181a1f3683dc45c9346c09a379679e1d13d16c", "parents": [ "2a15bfd79ced20a6d4cbf0a0a4c2fbb1444b9a44" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Jan 05 17:48:40 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sat Jan 20 08:07:23 2018 +0000" }, "message": "x86, mem: Pass the multi level page table layout in as a parameter.\n\nDon\u0027t get it from a global constant declared in an ISA header file.\n\nChange-Id: Ie19440abdd76500a5e12e6791e6f755ad9e95af3\nReviewed-on: https://gem5-review.googlesource.com/7344\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-by: Brandon Potter \u003cBrandon.Potter@amd.com\u003e\nReviewed-by: Alexandru Duțu \u003calexandru.dutu@amd.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "2a15bfd79ced20a6d4cbf0a0a4c2fbb1444b9a44", "tree": "d1fec5a31a00928dc9d5a3f4f05394236187d19c", "parents": [ "b1ade08b2da4a0b398b69ea4eb2de35b08941826" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Jan 05 15:01:00 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sat Jan 20 08:06:56 2018 +0000" }, "message": "arch, mem: Make the page table lookup function return a pointer.\n\nThis avoids having a copy in the lookup function itself, and the\ndeclaration of a lot of temporary TLB entry pointers in callers. The\ngpu TLB seems to have had the most dependence on the original signature\nof the lookup function, partially because it was relying on a somewhat\nunsafe copy to a TLB entry using a base class pointer type.\n\nChange-Id: I8b1cf494468163deee000002d243541657faf57f\nReviewed-on: https://gem5-review.googlesource.com/7343\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "b1ade08b2da4a0b398b69ea4eb2de35b08941826", "tree": "11bab348366bff951e63c7ed85da60567bec9aff", "parents": [ "6a98856affaaec393dfc6c8f67750c27858cc94c" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sun Jan 07 19:56:25 2018 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sat Jan 20 07:31:50 2018 +0000" }, "message": "base: Hide the BitUnion::__StorageType type.\n\nSince this type is now accessible through a clean interface, hide it\nfrom anybody that tries to peak around the curtain.\n\nChange-Id: I1257b6675a45b8648be459ad8e8d0f27a6feee6b\nReviewed-on: https://gem5-review.googlesource.com/7205\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" } ], "next": "6a98856affaaec393dfc6c8f67750c27858cc94c" }