)]}'
{
  "commit": "1dbcb2b729dadde02ef6cfb6dafbed6f71127b53",
  "tree": "7f8ee18ead39a4185a2f1e3160fb8aa2d2be8396",
  "parents": [
    "3396bd47266acf5741be76ec4a76e0e714bd5d4d"
  ],
  "author": {
    "name": "Christopher Daniel Emmons",
    "email": "chris.emmons@arm.com",
    "time": "Wed Jul 02 16:11:54 2014 -0700"
  },
  "committer": {
    "name": "Chris Emmons",
    "email": "chris.emmons@arm.com",
    "time": "Tue Jan 13 16:21:41 2015 -0600"
  },
  "message": "ARM: Fix broken coherency for DMA ops\n\nThis fixes a problem with dc zva/WriteInvalidate testing on v7. The\nThe system has coherent I/O and the kernel needs to know this.\n\nWhat would happen is the IO cache would hold DMA descriptor information\nin Exclusive state and the core would send uncacheable requests that\neffectively bypassed the coherence.  The IO device would then act on\nincoherent data.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e701a4d9aa591f02f729075e0727468fec8d69e5",
      "old_mode": 33188,
      "old_path": "arch/arm/include/asm/dma-mapping.h",
      "new_id": "d9c3cf681c534ed898129400ca7de464dca98d2c",
      "new_mode": 33188,
      "new_path": "arch/arm/include/asm/dma-mapping.h"
    },
    {
      "type": "modify",
      "old_id": "4afb376d9c7c13d07ea81502e17ba53f0554c122",
      "old_mode": 33188,
      "old_path": "arch/arm/include/asm/memory.h",
      "new_id": "f0c2bc48f6b0f64c5ea29f5cda0a29e2c7f268f4",
      "new_mode": 33188,
      "new_path": "arch/arm/include/asm/memory.h"
    }
  ]
}