|author||Rene de Jong <firstname.lastname@example.org>||Thu Sep 26 03:38:35 2013 -0700|
|committer||Chris Emmons <email@example.com>||Tue Jan 13 16:21:37 2015 -0600|
This patch introduces the possibility to read registers as 64 bit values. The gem5 NVMe device adheres to that; but the io.h functions do not. This has as consequence that the reading of those registers get split up in two transactions of 32 bits. This is not supported by the NVMe device. According to the NVMe spec, certain registers must be read as 64 bit values.