This patch introduces the possibility to read registers as 64 bit values.
The gem5 NVMe device adheres to that; but the io.h functions do not. This
has as consequence that the reading of those registers get split up in two
transactions of 32 bits. This is not supported by the NVMe device.

According to the NVMe spec, certain registers must be read as 64 bit values.
1 file changed