tree a0d6702fc1c45cba157a5734215c509fa4b216c6
parent 27547abf36af7964b53a8c9265e266df692d4806
author Jayachandran C <jchandra@broadcom.com> 1387624933 +0530
committer Ralf Baechle <ralf@linux-mips.org> 1390599586 +0100

MIPS: Netlogic: Add MSI support for XLP

Add MSI chip and MSIX chip definitions.

For MSI, we map the link interrupt to a MSI link IRQ which will
do a second level of dispatch based on the MSI status register.

The MSI chip definitions use the MSI enable register to enable
and disable the MSI irqs.

For MSI-X, we split the 32 available MSI-X vectors across the
four PCIe links (8 each). These PIC interrupts generate an IRQ
per link which uses a second level dispatch as well.

The MSI-X chip definition uses the standard functions to enable
and disable interrupts.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6270/