ARM: OMAP4: sleep/smp: switch CPU to BE if compiled for BE

If kernel operates in BE mode on device that has LE bootloader/ROM code,
we need to switch CPU to operate in BE mode before it will start to
access BE data. Generic secondary_startup function that is called from
OMAP specific secondary startup code will do the switch, but we need
to do it earlier because OMAP's secondary_startup code works with BE data.

Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 75e9295..75c98d4 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -17,6 +17,7 @@
 
 #include <linux/linkage.h>
 #include <linux/init.h>
+#include <asm/assembler.h>
 
 #include "omap44xx.h"
 
@@ -58,6 +59,12 @@
 	bne	hold
 
 	/*
+	 * ROM code operates in little endian mode, when we get control we
+	 * need to switch it back to big endian mode.
+	 */
+ARM_BE8(setend be)
+
+	/*
 	 * we've been released from the wait loop,secondary_stack
 	 * should now contain the SVC stack for this core
 	 */
@@ -75,6 +82,12 @@
 	bne	hold_2
 
 	/*
+	 * ROM code operates in little endian mode, when we get control we
+	 * need to switch it back to big endian mode.
+	 */
+ARM_BE8(setend be)
+
+	/*
 	 * GIC distributor control register has changed between
 	 * CortexA9 r1pX and r2pX. The Control Register secure
 	 * banked version is now composed of 2 bits:
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 8017016..f509dc5 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -260,6 +260,12 @@
  */
 ENTRY(omap4_cpu_resume)
 	/*
+	 * ROM code operates in little endian mode, when we get control we
+	 * need to switch it back to big endian mode.
+	 */
+ARM_BE8(setend	be)
+
+	/*
 	 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
 	 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
 	 * init and for CPU1, a secure PPA API provided. CPU0 must be ON