/*
 * Device Tree Source for the r8a7791 SoC
 *
 * Copyright (C) 2013 Renesas Electronics Corporation
 * Copyright (C) 2013 Renesas Solutions Corp.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/ {
	compatible = "renesas,r8a7791";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			clock-frequency = <1300000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
			clock-frequency = <1300000000>;
		};
	};

	gic: interrupt-controller@f1001000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0xf1001000 0 0x1000>,
			<0 0xf1002000 0 0x1000>,
			<0 0xf1004000 0 0x2000>,
			<0 0xf1006000 0 0x2000>;
		interrupts = <1 9 0xf04>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
				<1 14 0xf08>,
				<1 11 0xf08>,
				<1 10 0xf08>;
	};

	irqc0: interrupt-controller@e61c0000 {
		compatible = "renesas,irqc";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0 0xe61c0000 0 0x200>;
		interrupt-parent = <&gic>;
		interrupts = <0 0 4>,
			      <0 1 4>,
			      <0 2 4>,
			      <0 3 4>,
			      <0 12 4>,
			      <0 13 4>,
			      <0 14 4>,
			      <0 15 4>,
			      <0 16 4>,
			      <0 17 4>;
	};
};