)]}' { "log": [ { "commit": "b2af78846ad0fe2a0fb114bd3f55ef8d4eff4d7d", "tree": "f992f8e4f8fefadb057910ad916f803f5ce6c336", "parents": [ "735367964846f68990d0ab20fd69949734d6dfdb" ], "author": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:29:04 2015 -0600" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:40:34 2015 -0600" }, "message": "VExpress-gem5: Change non-server configs to use ION memory manager\n" }, { "commit": "735367964846f68990d0ab20fd69949734d6dfdb", "tree": "635f5adfa07cba63f97e4cf1681c1d38c150aa85", "parents": [ "56d230269aab613b58f50f4e8a00a46c0d69935d" ], "author": { "name": "Akash Bagdia", "email": "akash.bagdia@arm.com", "time": "Mon Aug 18 11:28:26 2014 +0100" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:40:34 2015 -0600" }, "message": "gem5-energy: Update dvfs config and dts files\n\nModified defconfig and dtses\u0027 to sync with latest mobile like gem5 baseline.\nUpdated gem5 cpufreq drivers to avoid registering when dvfs handler is\ndisabled in the gem5 hardware.\n" }, { "commit": "56d230269aab613b58f50f4e8a00a46c0d69935d", "tree": "0ca23f00740d93ef8aa84fb14135401405454704", "parents": [ "d5c6631953479f7084d0e352b194f66a1d4c1b19" ], "author": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Thu Aug 14 17:23:09 2014 -0500" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:40:33 2015 -0600" }, "message": "VExpress-gem5: Fix typo in dvfs dts file for energy-ctrl\n" }, { "commit": "d5c6631953479f7084d0e352b194f66a1d4c1b19", "tree": "d816ac415a16dfaac74276f2239a823b4a43ec6a", "parents": [ "d4aea5bf1c88f7b14e4b9e5b3fb7245a21cd48f3" ], "author": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Thu Jul 24 16:52:03 2014 -0500" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:40:33 2015 -0600" }, "message": "VExpress-gem5: Add default multi-core dts configs\n" }, { "commit": "d4aea5bf1c88f7b14e4b9e5b3fb7245a21cd48f3", "tree": "f179a5d9e1254b56cbfc1240ef5e7c33d3bb38cb", "parents": [ "4af3a5d9405128c21fa57a82f89f41a1c910ab36" ], "author": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Thu Jul 24 16:44:26 2014 -0500" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:40:32 2015 -0600" }, "message": "VExpress-gem5: Do not enable HDLCD by default in server config\n" }, { "commit": "4af3a5d9405128c21fa57a82f89f41a1c910ab36", "tree": "1084531f608d049b5e40e4f14e953d889c2a8e1a", "parents": [ "69ac35cf7a312006b4b0d7db8077aed0dbfbac32" ], "author": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Thu Jul 24 16:43:14 2014 -0500" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:40:32 2015 -0600" }, "message": "VExpress-gem5: Relocate HDLCD framebuffer to under 256MB\n" }, { "commit": "69ac35cf7a312006b4b0d7db8077aed0dbfbac32", "tree": "c465491a9cc8a949796a31cc605952ed75bac1a0", "parents": [ "1dbcb2b729dadde02ef6cfb6dafbed6f71127b53" ], "author": { "name": "Stephan Diestelhorst", "email": "stephan.diestelhorst@arm.com", "time": "Fri Jul 11 14:52:53 2014 +0100" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:40:15 2015 -0600" }, "message": "ARM: Adding support for an energy controller\n\nThe energy controller enables DVFS (dynamic voltage and frequency\nscaling support) of gem5 for up to 32 independent domains (or clusters).\nThe changes are modelled somewhat after the VExpress SPC component, but\nare specific to gem5.\n" }, { "commit": "1dbcb2b729dadde02ef6cfb6dafbed6f71127b53", "tree": "7f8ee18ead39a4185a2f1e3160fb8aa2d2be8396", "parents": [ "3396bd47266acf5741be76ec4a76e0e714bd5d4d" ], "author": { "name": "Christopher Daniel Emmons", "email": "chris.emmons@arm.com", "time": "Wed Jul 02 16:11:54 2014 -0700" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:41 2015 -0600" }, "message": "ARM: Fix broken coherency for DMA ops\n\nThis fixes a problem with dc zva/WriteInvalidate testing on v7. The\nThe system has coherent I/O and the kernel needs to know this.\n\nWhat would happen is the IO cache would hold DMA descriptor information\nin Exclusive state and the core would send uncacheable requests that\neffectively bypassed the coherence. The IO device would then act on\nincoherent data.\n" }, { "commit": "3396bd47266acf5741be76ec4a76e0e714bd5d4d", "tree": "185311e296a0388f2bb92802d5946cbc234f36c7", "parents": [ "b0d33131b7865d3e2d4188e7a0249f149c6cc233" ], "author": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Mon Dec 16 19:10:11 2013 -0600" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:40 2015 -0600" }, "message": "HDLcd: Default to 1080p and fix other video mode strings\n" }, { "commit": "b0d33131b7865d3e2d4188e7a0249f149c6cc233", "tree": "fbdb1be6dde84c5b65888581bfd8e2bb40468915", "parents": [ "48f097849da4370d7a055f11f6e679cda948657a" ], "author": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Dec 10 16:00:20 2013 -0600" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:40 2015 -0600" }, "message": "Enable early printk in gem5 platforms.\n" }, { "commit": "48f097849da4370d7a055f11f6e679cda948657a", "tree": "f432a8103fc8e7bb4a937b7dd2b8d297d86f10e9", "parents": [ "8b3cbd784a4f4369e23b1d1aba0b03bb4088df0a" ], "author": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Mon Dec 09 13:36:32 2013 -0600" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:39 2015 -0600" }, "message": "Enable HIMEM in vexpress_gem5_serverconfig.\n" }, { "commit": "8b3cbd784a4f4369e23b1d1aba0b03bb4088df0a", "tree": "1e95e8d77b51a0e4369de9e6c7f571743bca411a", "parents": [ "be668c661439c8fe18dcae636ee48f6085faf344" ], "author": { "name": "Rene de Jong", "email": "[mailto:rene.dejong@arm.com]", "time": "Mon Dec 09 13:32:15 2013 -0600" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:38 2015 -0600" }, "message": "Add architecture timer in DTB for gem5\n\nThis change in conjunction with changeset 2258 in gem5 (patch queue)\nmakes the architecture timer work.\n\nSigned-off-by: Rene de Jong \u003crene.dejong@arm.com\u003e\nSigned-off-by: Chris Emmons \u003cchris.emmons@arm.com\u003e\n" }, { "commit": "be668c661439c8fe18dcae636ee48f6085faf344", "tree": "7b1daabe3cd39b078768adeec1a9603f75dcc0b3", "parents": [ "75db1d846e1d67ff4d762b05fc9f50e581ccdf26" ], "author": { "name": "Geoffrey Blake", "email": "[mailto:geoffrey.blake@arm.com]", "time": "Fri Dec 06 12:47:57 2013 -0600" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:37 2015 -0600" }, "message": "Add in relevant bits for gem5 server configs\n\nAdd config options that fix MSI-X, coherent IO, etc.\n\nSigned-off-by: Geoffrey Blake \u003cgeobla01@arm.com\u003e\nSigned-off-by: Chris Emmons \u003cchris.emmons@arm.com\u003e\n" }, { "commit": "75db1d846e1d67ff4d762b05fc9f50e581ccdf26", "tree": "29de7856d7e0e0ffaf6ec10899cfbceb8bdadb94", "parents": [ "3b01425664496adc7bbb3c9c2033c7cdb74f7086" ], "author": { "name": "Rene de Jong", "email": "rene.dejong@arm.com", "time": "Thu Sep 26 03:38:35 2013 -0700" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:37 2015 -0600" }, "message": "This patch introduces the possibility to read registers as 64 bit values.\nThe gem5 NVMe device adheres to that; but the io.h functions do not. This\nhas as consequence that the reading of those registers get split up in two\ntransactions of 32 bits. This is not supported by the NVMe device.\n\nAccording to the NVMe spec, certain registers must be read as 64 bit values.\n" }, { "commit": "3b01425664496adc7bbb3c9c2033c7cdb74f7086", "tree": "ece2b06a8963791c055686a9f5cd72532e15b27b", "parents": [ "cefae65e433d5e804ff02eee86f72529f710216d" ], "author": { "name": "Stan Czerniawski", "email": "stan.czerniawski@arm.com", "time": "Thu Sep 26 03:12:05 2013 -0700" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:36 2015 -0600" }, "message": "Add (fixed) GICv2m driver from PDSW pci64 branch\n" }, { "commit": "cefae65e433d5e804ff02eee86f72529f710216d", "tree": "44d0669ef76b06e0aa9a381104f95587ce36c6b3", "parents": [ "8f2c84df0c5f7863aab681530e607bf7c9f9a707" ], "author": { "name": "Christopher Daniel Emmons", "email": "chris.emmons@arm.com", "time": "Thu Sep 05 07:11:57 2013 -0700" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:35 2015 -0600" }, "message": "EGIC: Changes GIC to allow boot of systems with more than 8 CPUs.\n" }, { "commit": "8f2c84df0c5f7863aab681530e607bf7c9f9a707", "tree": "4f8e61cb790cdbb54a6e8648ba9d4cfdccea4184", "parents": [ "8ffac22595c581a2640224e60c44419ac66914ac" ], "author": { "name": "Christopher Daniel Emmons", "email": "chris.emmons@arm.com", "time": "Wed Sep 04 16:12:26 2013 -0700" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:34 2015 -0600" }, "message": "vexpress-gem5: Large disk support added by default (CONFIG_LBDAF)\n" }, { "commit": "8ffac22595c581a2640224e60c44419ac66914ac", "tree": "57683a729bd0a201323e28d8400c60bbc2bfe498", "parents": [ "1df5d0f2c9c0869b5cbd7fc3e0eea4c7d636c2ba" ], "author": { "name": "Christopher Daniel Emmons", "email": "chris.emmons@arm.com", "time": "Fri May 31 15:19:36 2013 -0500" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:33 2015 -0600" }, "message": "HDLcd: Enable 4K resolution for gem5\n\nThis patch adds a 4K resolution option to the HDLcd controller\nwhich the real hardware is not capable of. This mode will be useful\nfor future-looking studies. The default resolution is unchanged;\nyou will need to update the dts file to enable 4K (see the new\ncomment in the dts file HDLcd controller section). You will also\nwant to change the HDLcd oscillator frequency in RealView.py to get\nthe frame rate you want as writing of the Versatile Express\noscillator registers currently doesn\u0027t have any effect on the gem5\nmodel. Tested with Android Jelly Bean.\n\nSigned-off-by: Christopher Daniel Emmons \u003cchris.emmons@arm.com\u003e\n" }, { "commit": "1df5d0f2c9c0869b5cbd7fc3e0eea4c7d636c2ba", "tree": "38532cc8a962a62348fa3caf27fe3288a78ef5c3", "parents": [ "9ab5f815800d5c562ad5e026db774c86cdca45f3" ], "author": { "name": "Christopher Daniel Emmons", "email": "chris.emmons@arm.com", "time": "Thu May 30 08:40:41 2013 -0700" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:32 2015 -0600" }, "message": "Streamline-gem5: Add support for Streamline on gem5\n\nSigned-off-by: Christopher Daniel Emmons \u003cchris.emmons@arm.com\u003e\n" }, { "commit": "9ab5f815800d5c562ad5e026db774c86cdca45f3", "tree": "2c0608ab387252ba18697f32749cb03ed3b7803a", "parents": [ "e588f77ab8458e84433819c238fde88f27032be8" ], "author": { "name": "Christopher Daniel Emmons", "email": "chris.emmons@arm.com", "time": "Wed May 29 13:42:10 2013 -0500" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:32 2015 -0600" }, "message": "UFS: Add UFS support\n\nUFS support is compiled into gem5 kernels by default. However, it\nis still disabled in the dts file by default. Uncommenting it in\nthe dts *should* make it work with an appropriately-configured\nsystem.\n\nSigned-off-by: Christopher Daniel Emmons \u003cchris.emmons@arm.com\u003e\n" }, { "commit": "e588f77ab8458e84433819c238fde88f27032be8", "tree": "d9f658edce6389d27582335f97d1a46a52741118", "parents": [ "3f169e1854aa8b7b555391b661f13349920cfbbb" ], "author": { "name": "Christopher Daniel Emmons", "email": "chris.emmons@arm.com", "time": "Wed May 29 13:05:31 2013 -0500" }, "committer": { "name": "Chris Emmons", "email": "chris.emmons@arm.com", "time": "Tue Jan 13 16:21:31 2015 -0600" }, "message": "Baseline retrofit of older pcie and gem5-specific support\n\nSigned-off-by: Christopher Daniel Emmons \u003cchris.emmons@arm.com\u003e\n" }, { "commit": "3f169e1854aa8b7b555391b661f13349920cfbbb", "tree": "7a9da9b82839e09d1f49b0116c422585a56ebff2", "parents": [ "6a8ec449204ca9cf070c8028b3eb419dfb060688", "041fa155e0a7a49d4084be684f855e2a32c17324" ], "author": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:53:07 2014 +0400" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:53:07 2014 +0400" }, "message": "Automatically merging tracking-ll-misc-fixes into merge-linux-linaro\n\nConflicting files:\narch/arm/mach-exynos/headsmp.S\n" }, { "commit": "6a8ec449204ca9cf070c8028b3eb419dfb060688", "tree": "30f13cd68271918be9abee43e3faf45d18b2a49e", "parents": [ "1e847a47af8d885e84cd278e037677677b7bde74", "8c7fa436cb712108c5e7ef249b03e667a3ecda0d" ], "author": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:35 2014 +0400" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:35 2014 +0400" }, "message": "Merge branch \u0027tracking-cortex-strings-arm64\u0027 into merge-linux-linaro\n" }, { "commit": "1e847a47af8d885e84cd278e037677677b7bde74", "tree": "6105c58a33a52fe377cef7aaaa5a1597bde4cd93", "parents": [ "2c2d3514946fd44ad37c3f5639115ee3c405ba05" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Fri Apr 11 20:46:52 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:33 2014 +0400" }, "message": "ARM: dts: hip04: enable only 1 core\n\nworkaround\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\n" }, { "commit": "2c2d3514946fd44ad37c3f5639115ee3c405ba05", "tree": "787e196a6386e30c56f8af16d3cb8c57517bfc93", "parents": [ "971342d7a90de74dc9ee60698d8002ed1dfdfaf4" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Thu Apr 03 21:30:19 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:33 2014 +0400" }, "message": "ata: ahci: support hisilicon device\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\nSigned-off-by: Kefeng Wang \u003ckefeng.wang@linaro.org\u003e\n" }, { "commit": "971342d7a90de74dc9ee60698d8002ed1dfdfaf4", "tree": "cc17c7a12b562f4f7ece49cca43bc0e8d3f909c2", "parents": [ "4fe75b321b14575bd2c2e622c8e17be205f24226" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Thu Apr 03 21:28:10 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:33 2014 +0400" }, "message": "ata: ahci: append new hflag\n\nAppend AHCI_HFLAG_NO_FBS to force turning off FBS flag.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "4fe75b321b14575bd2c2e622c8e17be205f24226", "tree": "a4db9dec668c19ddb168569c1c528a9228e4218a", "parents": [ "5877e8e9635c806d59839ef9edbd2c6a9977d66f" ], "author": { "name": "Kefeng Wang", "email": "kefeng.wang@linaro.org", "time": "Mon Mar 17 18:42:02 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:33 2014 +0400" }, "message": "ARM: dts: hip04: Add PMU support\n\nARM Performance Monitor Units are available on the hip04,\nadd the support in the dtsi.\n\nSimply tested with perf.\n\nSigned-off-by: Kefeng Wang \u003ckefeng.wang@linaro.org\u003e\n" }, { "commit": "5877e8e9635c806d59839ef9edbd2c6a9977d66f", "tree": "43c1a6f339e6814606e9d9c7d14b4508a752745b", "parents": [ "5f4c6b6471a230d8ca9369ad13dc2d2881a67b38" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Thu Mar 13 12:52:29 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:32 2014 +0400" }, "message": "Revert \"ARM: config: enable hi3xxx in multi_v7_defconfig\"\n\nThis reverts commit f1a34227dd2b46b2d86efc7856d19ef21a7b5bec.\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\n" }, { "commit": "5f4c6b6471a230d8ca9369ad13dc2d2881a67b38", "tree": "8b1798fd55d1fcbc315ee13a164572fd5a941f3f", "parents": [ "7780406002d41cb23a1b7bf8fad3796b2f6f79fc" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@gmail.com", "time": "Tue Mar 11 09:09:33 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:32 2014 +0400" }, "message": "config: append hip04\n\n./scripts/kconfig/merge_config.sh arch/arm/configs/multi_v7_defconfig linaro/configs/hip04.conf\n\nThe above command is used to produce the configuration file to bring up\nubuntu.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@gmail.com\u003e\n" }, { "commit": "7780406002d41cb23a1b7bf8fad3796b2f6f79fc", "tree": "0f6c2c2c37b128ad8d8d6171b9141a1f1b86bb9e", "parents": [ "b367e61cbd5a9f73f7edf5471ef9421ef75f5b58" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Tue Feb 18 17:29:46 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:32 2014 +0400" }, "message": "hip04: dts: add mdio resource\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\n" }, { "commit": "b367e61cbd5a9f73f7edf5471ef9421ef75f5b58", "tree": "9305099ad7f4083baed145408607b7ff1883351c", "parents": [ "4f748ab940180d8e48a2e2d283a16803806d83a5" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Tue Feb 18 17:28:11 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:31 2014 +0400" }, "message": "ether: support eth1\n\ntest:\nifconfig eth1 192.168.1.99; ping 192.168.1.10\n\nby default pc ethernet is 100M, also can work\nCan be change via command:\nhost:\nsudo ethtool eth0\nsudo ethtool -s eth0 duplex full speed 1000\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\n" }, { "commit": "4f748ab940180d8e48a2e2d283a16803806d83a5", "tree": "d011facb3532a7f3ee0eb17935ea054c8bd3db73", "parents": [ "0ba17dd387201b9c0c35fcefbc736d2e8a2c1d8d" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Tue Feb 18 17:26:18 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:31 2014 +0400" }, "message": "ether: add hip04_mdio.c\n\nAdd mdio interface, and reuse phy drivers/net/phy/marvell.c\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\n" }, { "commit": "0ba17dd387201b9c0c35fcefbc736d2e8a2c1d8d", "tree": "9785da7ff0c84b22a9a334c0418cb30d4400ca69", "parents": [ "6cfa217cad36b123b6a69a112420d36d85946e70" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Tue Jan 28 13:39:09 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:31 2014 +0400" }, "message": "hip04_defconfig: add CONFIG_HIP04_ETH\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\n" }, { "commit": "6cfa217cad36b123b6a69a112420d36d85946e70", "tree": "a19ace272ffb519c5497180914f09c406545fd1a", "parents": [ "c656c74d41353cb35fd1d9cd1d24b46f32200fc4" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Sun Jan 26 16:58:55 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:31 2014 +0400" }, "message": "hip04: dts: add ether resource\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\n" }, { "commit": "c656c74d41353cb35fd1d9cd1d24b46f32200fc4", "tree": "2df253496dfe6e2b6318b56c2250b448633c3167", "parents": [ "58e316646c0f6ef54b82da85020e017a7f587fec" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Sun Jan 26 16:41:12 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:30 2014 +0400" }, "message": "ether: add hip04_eth\n\ntest:\nifconfig eth0 192.168.10.1; ping 192.168.10.6 (host)\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\n" }, { "commit": "58e316646c0f6ef54b82da85020e017a7f587fec", "tree": "6370ee7e11c429b61dfd0e8105c169b90a40d17a", "parents": [ "115ba17f4dd07968eaafa256754b7d35197a19ee" ], "author": { "name": "Kefeng Wang", "email": "kefeng.wang@linaro.org", "time": "Mon Jan 20 20:00:47 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:30 2014 +0400" }, "message": "ARM: hip04: add specific sata vsemiphy init\n\npart1: add frame for specific sata vsemiphy init.\n\nSigned-off-by: Kefeng Wang \u003ckefeng.wang@linaro.org\u003e\n" }, { "commit": "115ba17f4dd07968eaafa256754b7d35197a19ee", "tree": "07d3b80d4761420a94b9382f6a40a559b8ad1402", "parents": [ "ebff48d31d04fbd81e158cfacba9ea847ba66f36" ], "author": { "name": "Kefeng Wang", "email": "kefeng.wang@linaro.org", "time": "Mon Jan 20 19:59:25 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:30 2014 +0400" }, "message": "ARM: dts: add sata device node\n\nAdd sata device node for hisi hip04 soc.\n\nSigned-off-by: Kefeng Wang \u003ckefeng.wang@linaro.org\u003e\n" }, { "commit": "ebff48d31d04fbd81e158cfacba9ea847ba66f36", "tree": "f0a17b4b6a7326d6fdb99c3edaf1bd59e495502c", "parents": [ "2591d232bf53a96d3080833d64e8ed89a343d809" ], "author": { "name": "Kefeng Wang", "email": "kefeng.wang@linaro.org", "time": "Mon Jan 20 19:57:40 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:29 2014 +0400" }, "message": "ahci: add support for Hisilicon sata\n\nThe hip04 SoC of hisilicon has an AHCI compliant SATA controller.\nThis patch adds the compatible string, and the controller is compliant\nwith the ahci 1.3 and sata 3.0 specification.\n\nISSUE: The hardware has defective designs.\n\nSigned-off-by: Kefeng Wang \u003ckefeng.wang@linaro.org\u003e\n" }, { "commit": "2591d232bf53a96d3080833d64e8ed89a343d809", "tree": "830e6540f5b31fee96b91b5f788eb08d9c4c274b", "parents": [ "376e8f5931bc793f6e1d1763131180f877a9eeea" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Mon Dec 23 18:05:52 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:29 2014 +0400" }, "message": "ARM: config: append hip04_defconfig\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "376e8f5931bc793f6e1d1763131180f877a9eeea", "tree": "7f09665ef3da8d32ff021651b266a67a7ea71d8f", "parents": [ "60273736f2bb6ca105e29fc9a23d95f22f10b5a9" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Mon Dec 23 10:16:21 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:29 2014 +0400" }, "message": "ARM: dts: add hip04-d01 platform support\n\nEnable SMP to support 4 cores. 16 cores could be supported at most.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "60273736f2bb6ca105e29fc9a23d95f22f10b5a9", "tree": "40bd773d0dc0bc231d9743581e134cabf05deb6d", "parents": [ "63b2af03a88d8a31721b62992b4f7f74a12287df" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Mon Dec 23 10:15:31 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:29 2014 +0400" }, "message": "ARM: hisi: add hip04-d01 support\n\nHiP04 is different from Hi3xxx SoC. LPAE is required by HiP04. HiP04 is\nCortex A15 SoC family.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "63b2af03a88d8a31721b62992b4f7f74a12287df", "tree": "11b4406fbef58cd07ecc9c2cdd41825fe812a585", "parents": [ "020b7ab7caeffe1566318755a36a859ea17cac74" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Tue Dec 24 21:38:26 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:28 2014 +0400" }, "message": "clk: hisi: remove static variable\n\nRemove the static variable. So these common clock register helper could\nbe used in more SoCs.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "020b7ab7caeffe1566318755a36a859ea17cac74", "tree": "b5a1ac1694dbfb4193caf98b0d51f0374f32d7df", "parents": [ "8b8534a0497127df7e9ef4f47e66f8940d321e8e" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Tue Dec 24 17:33:54 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:28 2014 +0400" }, "message": "clk: hip04: add clock driver\n\nNow only fixed rate clocks are appended into the clock driver.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "8b8534a0497127df7e9ef4f47e66f8940d321e8e", "tree": "6d36c4d6621dc4250c309a34e432e2673906cd02", "parents": [ "e0fea3f34333635ff5ae377b3354e8e0e795ad11" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Tue Dec 24 17:31:13 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:27 2014 +0400" }, "message": "clk: hisi: assign missing clk to table\n\nThe fixed rate and fixed factor clock isn\u0027t registered to clk table.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "e0fea3f34333635ff5ae377b3354e8e0e795ad11", "tree": "9f13ba921fdb270edc2253e8befef29c4201dab0", "parents": [ "615f56e8ddb6983601f9e0d438c1ee1d2f4c1241" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Fri Dec 20 15:01:41 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:27 2014 +0400" }, "message": "ARM: debug: add HiP04 debug uart\n\nAdd the support of Hisilicon HiP04 debug uart.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "615f56e8ddb6983601f9e0d438c1ee1d2f4c1241", "tree": "b4d70313b2ebc08feebe0b806a2120f128ed5c76", "parents": [ "ef597ea8326a8d442b31c1b64c667df6e8c71248" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Fri Oct 11 21:08:44 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:26 2014 +0400" }, "message": "ARM: hs: support hi3716-dkb board\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\nSigned-off-by: Zhang Mingjun \u003czhang.mingjun@linaro.org\u003e\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "ef597ea8326a8d442b31c1b64c667df6e8c71248", "tree": "9075f340b5bc2853e9aeaa01288852b190451870", "parents": [ "43fb1d6a029169847e412c9f20464124c8e98d4a" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Wed Aug 21 10:34:54 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:26 2014 +0400" }, "message": "ARM: hs: add clk-hi3716\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\nSigned-off-by: Zhang Mingjun \u003czhang.mingjun@linaro.org\u003e\n" }, { "commit": "43fb1d6a029169847e412c9f20464124c8e98d4a", "tree": "dcd94e25048fd1f17022398cd981314101dc692e", "parents": [ "bf8bf8600f70ad27148146ad6e137f4b8605171d" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Mon Mar 25 00:13:47 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:25 2014 +0400" }, "message": "rtc: add hi6421 rtc\n\nSupport hi6421 rtc function.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "bf8bf8600f70ad27148146ad6e137f4b8605171d", "tree": "34474268bd7e8b2dd13dcdbe35e52cdbe28c8720", "parents": [ "05a7a7788fcbb05171285944e13c350973009a15" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Fri Mar 15 15:23:48 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:25 2014 +0400" }, "message": "input: misc: add hi6421 onkey driver\n\nSupport Hi6421 PMIC powerkey driver.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "05a7a7788fcbb05171285944e13c350973009a15", "tree": "811ede6a4f3bd32aafdf91653716f386dae04bab", "parents": [ "3026427c42e0ac55403950402e1f43e98a5380de" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Mon Feb 10 18:05:25 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:22 2014 +0400" }, "message": "ARM: dts: correct L2 register address of Hi3620\n\nCorrect the register address of L2 controller in Hi3620 DTS file.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "3026427c42e0ac55403950402e1f43e98a5380de", "tree": "09cf30f2f2b4bf4d5195530c7936cd4ffe4e63bf", "parents": [ "3fe0a19dd4f7e13d02cca4a737b03edadd1a21d6" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Mon Feb 10 18:04:51 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:22 2014 +0400" }, "message": "ARM: hisi: enable PL310 L2 for hi3xxx\n\nEnable PL310 L2 cache for Hi3xxx SoC.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "3fe0a19dd4f7e13d02cca4a737b03edadd1a21d6", "tree": "50a2c83330dae3d3666dcc0618f336b1cf330810", "parents": [ "364da50736a9ac8016c65a50aa63235a7c7cde5f" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Wed Oct 23 14:32:52 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:22 2014 +0400" }, "message": "gpio: pl061: hook request if gpio-ranges avaiable\n\ngpio-ranges property could binds gpio to pinctrl. But there may be some\ngpios without pinctrl operation. So check whether gpio-ranges property\nexists in device node first.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "364da50736a9ac8016c65a50aa63235a7c7cde5f", "tree": "59cb932d274a82624547f454626e96d8d08ba0ae", "parents": [ "bd872d36be186fbc9009020b2d3efe32be60f836" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@linaro.org", "time": "Tue Oct 22 12:42:55 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:22 2014 +0400" }, "message": "gpio: pl061: add new property for gpio base\n\nIf gpio base number isn\u0027t specified, the gpio base will be find from\nthe end of gpio number. In order to keep with schematics, add a new\nproperty \"linux,gpio-base\" to specify the gpio number in DTS file.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "bd872d36be186fbc9009020b2d3efe32be60f836", "tree": "c16fd54c176400c15b56f5d82db5e56fe4717e8c", "parents": [ "9dd606aa0d86f0b35a7f9363036bfbc98dbf5fe0" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Fri Feb 07 10:28:02 2014 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:21 2014 +0400" }, "message": "ARM: dts: add mmc \u0026 i2c related resource\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\n" }, { "commit": "9dd606aa0d86f0b35a7f9363036bfbc98dbf5fe0", "tree": "4fc22ab73c7468c7322d4f718c53cbecd76ca6c4", "parents": [ "e11ce040a1fc556e00425a722de3b6c900e2450b" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Thu Aug 08 14:18:43 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:21 2014 +0400" }, "message": "Input: enable touch atmel_mXT224E\n\ntouchscreen:\nDevice Drivers ---\u003e\nInput device support ---\u003e\n[*] Touchscreens ---\u003e\n[*] Atmel mXT224E based touchscreens\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\n" }, { "commit": "e11ce040a1fc556e00425a722de3b6c900e2450b", "tree": "ef09d8b40ac7f80a3b56db7115e6b502a9b66394", "parents": [ "37e4edee5186248344363c4ec30c8538dfaa8e24" ], "author": { "name": "Guodong Xu", "email": "guodong.xu@linaro.org", "time": "Fri Aug 16 16:28:51 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:21 2014 +0400" }, "message": "regulator: hi6421: Add support to hi6421 regulators\n\nAdd support to hi6421 regulators. Hi6421 is a multi-functional PMIC\nmanufactured by HiSilicon Inc.\n\nSigned-off-by: Guodong Xu \u003cguodong.xu@linaro.org\u003e\nAcked-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "37e4edee5186248344363c4ec30c8538dfaa8e24", "tree": "e54e2f5df5ca1a8de5f1a30faf0d3ae6a53163ca", "parents": [ "9ff7383205dd3edb80c62e85eed0d28761928e3e" ], "author": { "name": "Guodong Xu", "email": "guodong.xu@linaro.org", "time": "Thu Aug 15 16:50:36 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:20 2014 +0400" }, "message": "mfd: Support HiSilicon Hi6421 PMIC\n\nAdd support of HiSilicon Hi6421 in mfd. Hi6421 is a power management and\ncodec IC from HiSilicon Inc., which includes regulators, codec, ADCs,\nCoulomb counter, etc. The way to communitcate with Hi6421 is through\nmemory mapped I/O ports.\n\nSigned-off-by: Guodong Xu \u003cguodong.xu@linaro.org\u003e\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@linaro.org\u003e\n" }, { "commit": "9ff7383205dd3edb80c62e85eed0d28761928e3e", "tree": "70f31ff59c0a4fe6a3510b7086e916de57b4f2bc", "parents": [ "987129f97caa13a328d3e3b49e94ce3fd72fc133" ], "author": { "name": "Zhangfei Gao", "email": "zhangfei.gao@linaro.org", "time": "Wed Dec 11 14:40:59 2013 +0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:20 2014 +0400" }, "message": "clk: hisilicon: add hi3620_mmc_clks\n\nSuggest by Arnd: abstract mmc tuning as clock behavior,\nalso because different soc have different tuning method and registers.\nhi3620_mmc_clks is added to handle mmc clock specifically on hi3620.\n\nSigned-off-by: Zhangfei Gao \u003czhangfei.gao@linaro.org\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nAcked-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\n" }, { "commit": "987129f97caa13a328d3e3b49e94ce3fd72fc133", "tree": "e6bb26e3f30e00878525c8f68d800d0ebb5085c9", "parents": [ "646173fbe7626111c314e34f2b439ea79f0bc767" ], "author": { "name": "Taras Kondratiuk", "email": "taras.kondratiuk@linaro.org", "time": "Fri Nov 08 18:29:29 2013 +0000" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:12 2014 +0400" }, "message": "ARM: kprobes-test: Workaround GAS .align bug\n\nBy default if no fill symbol is given to .align directive in a code\nsection it fills gap with NOPs. If previous fragment is not\ninstruction-aligned, additional pre-alignment is done by zero bytes\nbefore NOPs. These zero bytes are marked as data by special symbol $d in\nsymbol table. Unfortunately GAS assumes that there is only code in the\ncode section so it \"puts back\" code symbol $a at the end of this\npre-alignment. So if there is some data after alignment it will be\ninterpreted as code and will be swapped back to LE for BE8 system during\na final linking.\n\nIf explicit fill value is given to .align, the NOP-padding code is\nskipped and symbol table does not get messed-up.\n\nSo the workaround for this issue:\nUse explicit fill value if data should be aligned in the code section.\n\nAcked-by: Ben Dooks \u003cben.dooks@codethink.co.uk\u003e\nAcked-by: Jon Medhurst \u003ctixy@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "646173fbe7626111c314e34f2b439ea79f0bc767", "tree": "6dcb593ff463d7bddbf09e30787c347d9783494f", "parents": [ "833088f40a3d3549c49208ffcd2305aefbfdf8ad" ], "author": { "name": "Ben Dooks", "email": "ben.dooks@codethink.co.uk", "time": "Fri Nov 08 18:29:28 2013 +0000" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:11 2014 +0400" }, "message": "ARM: kprobes-test: use \u003casm/opcodes.h\u003e for Thumb instruction building\n\nThe kprobes test will build certain instructions incorrectly if building\nbig endian as .word/.short output gets endian-swapped by the linker.\nChange to using \u003casm/opcodes.h\u003e and __inst_thumbXX() to produce instructions.\n\nAcked-by: Jon Medhurst \u003ctixy@linaro.org\u003e\nSigned-off-by: Ben Dooks \u003cben.dooks@codethink.co.uk\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "833088f40a3d3549c49208ffcd2305aefbfdf8ad", "tree": "d618019db20b98fc8cc0253646e0b345a126c641", "parents": [ "ce35aacdfe5d8f53c5110949204d5c8ae90b880d" ], "author": { "name": "Ben Dooks", "email": "ben.dooks@codethink.co.uk", "time": "Fri Nov 08 18:29:27 2013 +0000" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:11 2014 +0400" }, "message": "ARM: kprobes-test: use \u003casm/opcodes.h\u003e for ARM instruction building\n\nThe kprobes test will build certain instructions incorrectly if building\nbig endian as .word output gets endian-swapped by the linker. Change to\nusing \u003casm/opcodes.h\u003e and __inst_arm() to produce instructions.\n\nAcked-by: Jon Medhurst \u003ctixy@linaro.org\u003e\nSigned-off-by: Ben Dooks \u003cben.dooks@codethink.co.uk\u003e\n[taras.kondratiuk@linaro.org: fixed unsupported coprocessor instructions]\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "ce35aacdfe5d8f53c5110949204d5c8ae90b880d", "tree": "558316ad64e0e4b43f4e6672c9f848e5e40f54f3", "parents": [ "a22480b9c7f9e7662ce317830f1cb78d54493636" ], "author": { "name": "Ben Dooks", "email": "ben.dooks@codethink.co.uk", "time": "Fri Nov 08 18:29:26 2013 +0000" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:08 2014 +0400" }, "message": "ARM: kprobes-test: use \u003casm/opcodes.h\u003e for instruction accesses\n\nEnsure we read instructions in the correct endian-ness by using\nthe \u003casm/opcodes.h\u003e helper to transform them as necessary.\n\nAcked-by: Jon Medhurst \u003ctixy@linaro.org\u003e\nSigned-off-by: Ben Dooks \u003cben.dooks@codethink.co.uk\u003e\n[taras.kondratiuk@linaro.org: fix next_instruction() function]\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "a22480b9c7f9e7662ce317830f1cb78d54493636", "tree": "248fa116a304a24a6a42087863131fe81f714250", "parents": [ "0bce083cf83df4120d08e62b09d631f2b806c83e" ], "author": { "name": "Ben Dooks", "email": "ben.dooks@codethink.co.uk", "time": "Fri Nov 08 18:29:25 2013 +0000" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:08 2014 +0400" }, "message": "ARM: kprobes: fix instruction fetch order with \u003casm/opcodes.h\u003e\n\nIf we are running BE8, the data and instruction endianness do not\nmatch, so use \u003casm/opcodes.h\u003e to correctly translate memory accesses\ninto ARM instructions.\n\nAcked-by: Jon Medhurst \u003ctixy@linaro.org\u003e\nSigned-off-by: Ben Dooks \u003cben.dooks@codethink.co.uk\u003e\n[taras.kondratiuk@linaro.org: fixed Thumb instruction fetch order]\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "0bce083cf83df4120d08e62b09d631f2b806c83e", "tree": "44001fb4c2702f3b8370fea6c42e12b8f6bf8ba0", "parents": [ "d4b414996986f8c92806e1ec5ad44278f211b1b6" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Thu Nov 07 10:32:09 2013 -0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:06 2014 +0400" }, "message": "ARM: OMAP4: enable big endian support\n\nPrevious patches fixed big endian issues in OMAP4 code,\nso mark it as one that supports big endian\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "d4b414996986f8c92806e1ec5ad44278f211b1b6", "tree": "09fcb87108f6a0c7f998ecd40bc7a6d806609831", "parents": [ "2e640429c2bb977cff44e470849bc73b4be6310c" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Thu Nov 07 10:32:08 2013 -0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:05 2014 +0400" }, "message": "ARM: OMAP4: sleep/smp: switch CPU to BE if compiled for BE\n\nIf kernel operates in BE mode on device that has LE bootloader/ROM code,\nwe need to switch CPU to operate in BE mode before it will start to\naccess BE data. Generic secondary_startup function that is called from\nOMAP specific secondary startup code will do the switch, but we need\nto do it earlier because OMAP\u0027s secondary_startup code works with BE data.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "2e640429c2bb977cff44e470849bc73b4be6310c", "tree": "4ea9657d5786edbc18b533c7a5c1a9e9701639bd", "parents": [ "2556a265c5b18b3e071038dd6914f2980d7f9fb4" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Thu Nov 07 10:32:07 2013 -0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:05 2014 +0400" }, "message": "ARM: OMAP4: sleep: byteswap data for big-endian\n\nAssembler functions defined in sleep44xx.S need to byteswap values\nafter read / before write from h/w register if code compiled in big\nendian mode. Simple change to do \u0027rev x, x\u0027 before str instruction\nand after ldr instruction that deals with h/w registers.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "2556a265c5b18b3e071038dd6914f2980d7f9fb4", "tree": "e303f222c30752b777924566df136d2aa6486afd", "parents": [ "6b4e6acded061e4d0d79428f0155d0fcb23e55d6" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Mon Nov 11 19:23:24 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:05 2014 +0400" }, "message": "ARM: OMAP: debug-leds: raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "6b4e6acded061e4d0d79428f0155d0fcb23e55d6", "tree": "e1f66b9242881a4ca42a9b181fcdadf92501b814", "parents": [ "0419045875f97dc5e75b525e2d6d07b99a1d91f0" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Mon Nov 11 16:20:26 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:05 2014 +0400" }, "message": "ARM: OMAP: counter-32k: raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "0419045875f97dc5e75b525e2d6d07b99a1d91f0", "tree": "c7a9c7c8c31c8a212b5efc945ee426d0ea8849a9", "parents": [ "8a1e3aebb39317304ac094bb5a0286869837efbf" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Mon Nov 11 16:16:38 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:04 2014 +0400" }, "message": "ARM: OMAP: dmtimer: raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "8a1e3aebb39317304ac094bb5a0286869837efbf", "tree": "ce48eba86d2724aa79786cc3601a4765a58f3f26", "parents": [ "f8a8221ff06d9283857919ae7567d90c9624aa14" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Mon Nov 11 17:27:11 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:04 2014 +0400" }, "message": "ARM: OMAP2+: raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "f8a8221ff06d9283857919ae7567d90c9624aa14", "tree": "d1771501cb9e85920b69c1ec0992dd5d0e740d57", "parents": [ "bf15f7f85404a11281c08a666d605ff536eb6e54" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Fri Nov 08 19:44:09 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:04 2014 +0400" }, "message": "usb: musb: raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "bf15f7f85404a11281c08a666d605ff536eb6e54", "tree": "436980820d35bda3d53ff9e1458fa33848fe3c24", "parents": [ "4ac5fd962358e9b9046c41c2652b884a201f3fb8" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Fri Nov 08 19:30:38 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:03 2014 +0400" }, "message": "USB: ehci-omap: raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "4ac5fd962358e9b9046c41c2652b884a201f3fb8", "tree": "a73f21a51e4c7c2b79685c70864bc4c7c8be442d", "parents": [ "cf88ebba2f66f69d621a9b727da744613646c6a2" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Fri Nov 08 18:15:39 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:03 2014 +0400" }, "message": "Input: omap-keypad - raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "cf88ebba2f66f69d621a9b727da744613646c6a2", "tree": "906d6b76fe7939aa98c744103c80f6494cf5571a", "parents": [ "f8032dd3adf634e0ce4c72da99cccd34f20ffca6" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Fri Nov 08 18:10:47 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:03 2014 +0400" }, "message": "crypto: omap-sham - raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "f8032dd3adf634e0ce4c72da99cccd34f20ffca6", "tree": "ad116b919f42f93d2e03748175cf6a5a83afbe71", "parents": [ "7fe284b2c40bbc89590be53d196df01c10bec1aa" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Fri Nov 08 18:07:16 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:03 2014 +0400" }, "message": "crypto: omap-aes - raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "7fe284b2c40bbc89590be53d196df01c10bec1aa", "tree": "53c6b9953ded1cb1abd75017d49b42689e36988a", "parents": [ "275a08dcae876c3fd3e3cb10e0d71681753f1528" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Fri Nov 08 18:01:31 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:02 2014 +0400" }, "message": "hwrng: omap - raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "275a08dcae876c3fd3e3cb10e0d71681753f1528", "tree": "d9677b92fe26068b34e3804cb9f2f8f21aed1041", "parents": [ "eb01aac61841e2bfaa4478e3d7715b97e6bcbe76" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Fri Nov 08 17:56:14 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:02 2014 +0400" }, "message": "drivers: bus: omap_l3: raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "eb01aac61841e2bfaa4478e3d7715b97e6bcbe76", "tree": "59bff2ef7150ea30bf0957c568355febc768df2c", "parents": [ "17dc476aaa5fb375d60bcd9584819be75f79879e" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Fri Nov 08 15:23:19 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:02 2014 +0400" }, "message": "mmc: omap: raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "17dc476aaa5fb375d60bcd9584819be75f79879e", "tree": "70397317522b3fa423f9ad1a829307d09cf8f779", "parents": [ "e7ad3a8e57b4431331b890704b37fd0afd2464b5" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Fri Nov 08 15:10:10 2013 +0200" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:00 2014 +0400" }, "message": "OMAPDSS: raw read and write endian fix\n\nAll OMAP IP blocks expect LE data, but CPU may operate in BE mode.\nNeed to use endian neutral functions to read/write h/w registers.\nI.e instead of __raw_read[lw] and __raw_write[lw] functions code\nneed to use read[lw]_relaxed and write[lw]_relaxed functions.\nIf the first simply reads/writes register, the second will byteswap\nit if host operates in BE mode.\n\nChanges are trivial sed like replacement of __raw_xxx functions\nwith xxx_relaxed variant.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\nSigned-off-by: Taras Kondratiuk \u003ctaras.kondratiuk@linaro.org\u003e\n" }, { "commit": "e7ad3a8e57b4431331b890704b37fd0afd2464b5", "tree": "4ccaf92b753cb1e7eea6e501ec8b3fa00a16baa5", "parents": [ "6eaad95a468ca5a9dc1b3d9bff96b6b07a03a9d3" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Mon Nov 04 16:11:08 2013 -0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:00 2014 +0400" }, "message": "exynos: enable big endian support\n\nPrevious patches fixed endian neutral issues in Arndale BSP, so mark it as one\nthat supports big endian\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\n" }, { "commit": "6eaad95a468ca5a9dc1b3d9bff96b6b07a03a9d3", "tree": "8aac702604af90a7ece2aa05916acbb009730b3a", "parents": [ "c6a8674376e6c990eb478badfbfde8016297c21d" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Fri Nov 08 23:08:42 2013 -0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:52:00 2014 +0400" }, "message": "exynos: serial clear and set big endian fix\n\nSamsung serial driver uses __set_bit and __clear_bit functions directly with\nh/w registers. But these functions are not endian neutral. In case of BE host\nbefore operation on the bit byte swap is needed and byte swap is required\nafter operation on the bit is complete. Patch creates and use __hw_set_bit\nand __hw_clear_bit, that in case of LE just call __set_bit and __clear_bit,\nbut in case of BE they do required byteswaps\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\n" }, { "commit": "c6a8674376e6c990eb478badfbfde8016297c21d", "tree": "ab5f2fef17b370d08ca0a0f2d191a9f67eb856bf", "parents": [ "7d313effe07583ce7e5743f441b58878f3f3f810" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Sat Nov 02 11:52:50 2013 -0700" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:59 2014 +0400" }, "message": "exynos: secondary_startup endian fix\n\nIf kernel operates in BE mode on board that has LE bootloader/rom code, we need\nto switch CPU to operate in BE mode as soon as possible. generic\nsecondary_startup that is called from exynos specific secondary startup code\nwill do the switch, but we need it to do earlier because exynos specific\nsecondary_startup code works with BE data.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\n" }, { "commit": "7d313effe07583ce7e5743f441b58878f3f3f810", "tree": "c74c95a4480e0db43eb084d991b3be939e9d88fe", "parents": [ "ea74f1e7bb2baf4f32aa03702792d1de031c78d9" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Sat Nov 02 11:49:39 2013 -0700" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:59 2014 +0400" }, "message": "exynos: boot serial endian fix\n\nuncompress serial line write utils need to use endian neutral functions to\nread h/w register - i.e in case of BE host byteswap is needed. Fix uart_rd,\nuart_wr and serial chip fifo related macros\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\n" }, { "commit": "ea74f1e7bb2baf4f32aa03702792d1de031c78d9", "tree": "172767fa965ac1f35fcd0758942851fca4ae7e10", "parents": [ "aeeb7354d6fb29705af44c6420a223f838ccabc9" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Sun Sep 29 21:19:14 2013 -0700" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:58 2014 +0400" }, "message": "exynos: driver raw read and write endian fix\n\nNeed to use endian neutral functions to read/write LE h/w registers. I.e\ninstead of __raw_read[lw] and _raw_write[lw] functions code need to use\nread[lw]_relaxed and write[lw]_relaxed functions. If the first just\nread/write register with memory barrier, the second will byteswap it if host\noperates in BE mode.\n\nThis patch covers drivers used by arndale board where all changes are trivial,\nsed like replacement of __raw_xxx functions with xxx_relaxed variant.\nLiterally this sed program was used to make the change:\n\ns|__raw_readl|readl_relaxed|g\ns|__raw_writel|writel_relaxed|g\ns|__raw_readw|readw_relaxed|g\ns|__raw_writew|writew_relaxed|g\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\n" }, { "commit": "aeeb7354d6fb29705af44c6420a223f838ccabc9", "tree": "c3b72b78d9bc11d41d48f20d2bccff3d5e2128f4", "parents": [ "05440ad637ca2d0921d9a908bb02b99abdedf847" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Fri Nov 08 15:58:46 2013 -0800" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:57 2014 +0400" }, "message": "mmc: dw_mmc endian fix\n\nNeed to use endian neutral functions to read/write h/w registers. I.e\n__raw_readl replaced with readl_relaxed and __raw_writel replaced with\nwritel_relaxed. The relaxed version of function will read/write LE h/w\nregister and byteswap it if host operates in BE mode.\n\nHowever in case of this file __raw_read(wlq) and __raw_write(wlq) are also\nused to transfer data from uchar buffer into h/w mmc host register. And in\nthis case byteswap is not need - bytes of data buffer should go into h/w\nregister in the same order as they are in memory. So we need to split control\nmci_readl/mci_writel macros from one that operates on data mci_readw_data,\nmci_readl_data, mci_readq_data, mci_writew, mci_writel_data, mci_writeq_data.\nThe latter one do not do byte swaps.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\n" }, { "commit": "05440ad637ca2d0921d9a908bb02b99abdedf847", "tree": "156446f65807f167e4c582dc813485103c710001", "parents": [ "88c9d2670ceb7d062c4fb3ed770210d61701e8f8" ], "author": { "name": "Victor Kamensky", "email": "victor.kamensky@linaro.org", "time": "Mon Jul 29 22:03:27 2013 -0700" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:57 2014 +0400" }, "message": "mtd: map.h endian fix\n\nNeed to use endian neutral functions to read/write LE h/w registers. I.e\ninsted of __raw_readl and _raw_writel, readl_relaxed and writel_relaxed. If\nthe first just read/write register with memory barrier, the second will\nbyteswap it if host operates in BE mode.\n\nSigned-off-by: Victor Kamensky \u003cvictor.kamensky@linaro.org\u003e\n" }, { "commit": "88c9d2670ceb7d062c4fb3ed770210d61701e8f8", "tree": "64680b326924b85ab3bd211c1b81577ca530aa0d", "parents": [ "ef8b72919a828daff768c18a578052082e3afa80" ], "author": { "name": "Tushar Behera", "email": "tushar.behera@linaro.org", "time": "Tue Mar 25 17:29:25 2014 +0530" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:53 2014 +0400" }, "message": "ARM: dts: Add pmu nodes for Exynos5420\n\nAdding perf nodes for A15 cores.\n\nSigned-off-by: Tushar Behera \u003ctushar.behera@linaro.org\u003e\n" }, { "commit": "ef8b72919a828daff768c18a578052082e3afa80", "tree": "52457c972367812f0ceb285d21199e663e689bb8", "parents": [ "e6882b51209db993c1e48e612d7e4d588051ee32" ], "author": { "name": "Rahul Sharma", "email": "Rahul.Sharma@samsung.com", "time": "Mon Mar 17 19:35:00 2014 +0530" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:53 2014 +0400" }, "message": "ARM: EXYNOS: Enable iommu support for Exynos5\n\nSigned-off-by: Rahul Sharma \u003cRahul.Sharma@samsung.com\u003e\nSigned-off-by: Tushar Behera \u003ctushar.behera@linaro.org\u003e\n" }, { "commit": "e6882b51209db993c1e48e612d7e4d588051ee32", "tree": "a2245fd291a866db4d19e3a3d0dfe589ceae2153", "parents": [ "fe20a7bcf15607e2699737d8e56f62f9089f85ae" ], "author": { "name": "Cho KyongHo", "email": "pullip.cho@samsung.com", "time": "Tue Aug 06 20:00:17 2013 +0900" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:52 2014 +0400" }, "message": "ARM: dts: Add description of System MMU of Exynos SoCs\n\nThis patch adds dts entries for the System MMU devices found on\nExynos4 and Exynos5 SoC series and the System MMU binding\ndocumentation.\n\nCC: Rob Herring \u003crobherring2@gmail.com\u003e\nCC: Sylwester Nawrocki \u003cs.nawrocki@samsung.com\u003e\nSigned-off-by: Cho KyongHo \u003cpullip.cho@samsung.com\u003e\n" }, { "commit": "fe20a7bcf15607e2699737d8e56f62f9089f85ae", "tree": "f6dcfd3934935cf86a825a35f21b1f6034287a94", "parents": [ "810cef546d5f62aa9180a0e9addf4a7467dbc335" ], "author": { "name": "Cho KyongHo", "email": "pullip.cho@samsung.com", "time": "Mon Mar 10 18:14:04 2014 +0900" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:52 2014 +0400" }, "message": "iommu/exynos: enhanced error messages\n\nSome redundant error message is removed and some error messages\nare changed to error level from debug level.\n\nSigned-off-by: Cho KyongHo \u003cpullip.cho@samsung.com\u003e\n" }, { "commit": "810cef546d5f62aa9180a0e9addf4a7467dbc335", "tree": "9fcfda51d5cb9bfdbc4aefc141e103a08268588f", "parents": [ "544bc26c36d78994ea272a6ac2ea253ca14332c0" ], "author": { "name": "Cho KyongHo", "email": "pullip.cho@samsung.com", "time": "Mon Mar 10 17:28:54 2014 +0900" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:52 2014 +0400" }, "message": "iommu/exynos: apply workaround of caching fault page table entries\n\nThis patch contains 2 workaround for the System MMU v3.x.\n\nSystem MMU v3.2 and v3.3 has FLPD cache that caches first level page\ntable entries to reduce page table walking latency. However, the\nFLPD cache is filled with a first level page table entry even though\nit is not accessed by a master H/W because System MMU v3.3\nspeculatively prefetches page table entries that may be accessed\nin the near future by the master H/W.\nThe prefetched FLPD cache entries are not invalidated by iommu_unmap()\nbecause iommu_unmap() only unmaps and invalidates the page table\nentries that is mapped.\n\nBecause exynos-iommu driver discards a second level page table when\nit needs to be replaced with another second level page table or\na first level page table entry with 1MB mapping, It is required to\ninvalidate FLPD cache that may contain the first level page table\nentry that points to the second level page table.\n\nAnother workaround of System MMU v3.3 is initializing the first level\npage table entries with the second level page table which is filled\nwith all zeros. This prevents System MMU prefetches \u0027fault\u0027 first\nlevel page table entry which may lead page fault on access to 16MiB\nwide.\n\nSystem MMU 3.x fetches consecutive page table entries by a page\ntable walking to maximize bus utilization and to minimize TLB miss\npanelty.\nUnfortunately, functional problem is raised with the fetching behavior\nbecause it fetches \u0027fault\u0027 page table entries that specifies no\ntranslation information and that a valid translation information will\nbe written to in the near future. The logic in the System MMU generates\npage fault with the cached fault entries that is no longer coherent\nwith the page table which is updated.\n\nThere is another workaround that must be implemented by I/O virtual\nmemory manager: any two consecutive I/O virtual memory area must have\na hole between the two that is larger than or equal to 128KiB.\nAlso, next I/O virtual memory area must be started from the next\n128KiB boundary.\n\n0 128K 256K 384K 512K\n|-------------|---------------|-----------------|----------------|\n|area1----------------\u003e|.........hole...........|\u003c--- area2 -----\n\nThe constraint is depicted above.\nThe size is selected by the calculation followed:\n - System MMU can fetch consecutive 64 page table entries at once\n 64 * 4KiB \u003d 256KiB. This is the size between 128K ~ 384K of the\n above picture. This style of fetching is \u0027block fetch\u0027. It fetches\n the page table entries predefined consecutive page table entries\n including the entry that is the reason of the page table walking.\n - System MMU can prefetch upto consecutive 32 page table entries.\n This is the size between 256K ~ 384K.\n\nSigned-off-by: Cho KyongHo \u003cpullip.cho@samsung.com\u003e\n" }, { "commit": "544bc26c36d78994ea272a6ac2ea253ca14332c0", "tree": "d15b3b1629c7f715f4291a010251e042527988e1", "parents": [ "181b096b451a201fbeab4a40a6629360c465298b" ], "author": { "name": "Cho KyongHo", "email": "pullip.cho@samsung.com", "time": "Mon Mar 10 16:34:12 2014 +0900" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:51 2014 +0400" }, "message": "iommu/exynos: use simpler function to get MMU version\n\nThis commit changes the function to get MMU version simpler.\n\nSigned-off-by: Cho KyongHo \u003cpullip.cho@samsung.com\u003e\n" }, { "commit": "181b096b451a201fbeab4a40a6629360c465298b", "tree": "9dbb4d50c2eb49b33d328a997a6908279d68e6d0", "parents": [ "0af1858f08126b23cb63c9cfb1e2080be0533d86" ], "author": { "name": "Cho KyongHo", "email": "pullip.cho@samsung.com", "time": "Sun Mar 09 17:49:08 2014 +0900" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:51 2014 +0400" }, "message": "iommu/exynos: use exynos-iommu specific typedef\n\nThis commit introduces sysmmu_pte_t for page table entries and\nsysmmu_iova_t vor I/O virtual address that is manipulated by\nexynos-iommu driver. The purpose of the typedef is to remove\ndependencies to the driver code from the change of CPU architecture\nfrom 32 bit to 64 bit.\n\nSigned-off-by: Cho KyongHo \u003cpullip.cho@samsung.com\u003e\n" }, { "commit": "0af1858f08126b23cb63c9cfb1e2080be0533d86", "tree": "6a54a60d6e5f5b2339d2ea68529ea5712acc6a7e", "parents": [ "6ec091d4112a6f90629b9a62cf4342d5f6db8fec" ], "author": { "name": "Cho KyongHo", "email": "pullip.cho@samsung.com", "time": "Tue Feb 18 14:28:56 2014 +0900" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:50 2014 +0400" }, "message": "iommu/exynos: fix address handling\n\nUse of __pa and __va macro is changed to virt_to_phys and phys_to_virt\nwhich are recommended in driver code. printk formatting of physical\naddress is also fixed to %pa.\n\nSigned-off-by: Cho KyongHo \u003cpullip.cho@samsung.com\u003e\n" }, { "commit": "6ec091d4112a6f90629b9a62cf4342d5f6db8fec", "tree": "e421ca3a411d3b6760e9a1a8eeaef14222fe7c75", "parents": [ "8a1a91b57a3f2d9906466dc2dd0c99e99947a0a4" ], "author": { "name": "Antonios Motakis", "email": "a.motakis@virtualopensystems.com", "time": "Mon Sep 16 20:13:48 2013 +0900" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:48 2014 +0400" }, "message": "iommu/exynos: add devices attached to the System MMU to an IOMMU group\n\nPatch written by Antonios Motakis \u003ca.motakis@virtualopensystems.com\u003e:\n\nIOMMU groups are expected by certain users of the IOMMU API,\ne.g. VFIO. Since each device is behind its own System MMU, we\ncan allocate a new IOMMU group for each device.\n\nReviewd-by: Cho KyongHo \u003cpullip.cho@samsung.com\u003e\nSigned-off-by: Antonios Motakis \u003ca.motakis@virtualopensystems.com\u003e\n" }, { "commit": "8a1a91b57a3f2d9906466dc2dd0c99e99947a0a4", "tree": "0f3d87175d9d5d040b5d17e09e98783ff045d5d6", "parents": [ "9cc69cd5f33940fbf19fbff220f1c28f6e68867d" ], "author": { "name": "Cho KyongHo", "email": "pullip.cho@samsung.com", "time": "Mon Sep 09 19:34:02 2013 +0900" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:45 2014 +0400" }, "message": "iommu/exynos: change rwlock to spinlock\n\nSince acquiring read_lock is not more frequent than write_lock, it is\nnot beneficial to use rwlock, this commit changes rwlock to spinlock.\n\nReviewed-by: Grant Grundler \u003cgrundler@chromium.org\u003e\nSigned-off-by: Cho KyongHo \u003cpullip.cho@samsung.com\u003e\n" }, { "commit": "9cc69cd5f33940fbf19fbff220f1c28f6e68867d", "tree": "3adb2f02480e99e549d908cfc53e2f611a112f2c", "parents": [ "5e876afbe11640da1550d3cc867c6b5c2005a78e" ], "author": { "name": "Cho KyongHo", "email": "pullip.cho@samsung.com", "time": "Sun Mar 09 21:27:53 2014 +0900" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:43 2014 +0400" }, "message": "iommu/exynos: allow having multiple System MMUs for a master H/W\n\nSome master device descriptor like fimc-is which is an abstraction\nof very complex H/W may have multiple System MMUs. For those devices,\nthe design of the link between System MMU and its master H/W is needed\nto be reconsidered.\n\nA link structure, sysmmu_list_data is introduced that provides a link\nto master H/W and that has a pointer to the device descriptor of a\nSystem MMU. Given a device descriptor of a master H/W, it is possible\nto traverse all System MMUs that must be controlled along with the\nmaster H/W.\n\nSigned-off-by: Cho KyongHo \u003cpullip.cho@samsung.com\u003e\n" }, { "commit": "5e876afbe11640da1550d3cc867c6b5c2005a78e", "tree": "eb4371bc964073ee2b785dbd912f9e6aa02f8db5", "parents": [ "fe8e4fd8ee9313ed6a97461b90c3ae24f64b557e" ], "author": { "name": "Cho KyongHo", "email": "pullip.cho@samsung.com", "time": "Wed Aug 07 09:33:22 2013 +0900" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:42 2014 +0400" }, "message": "iommu/exynos: add support for power management subsystems.\n\nThis adds support for Suspend to RAM and Runtime Power Management.\n\nSince System MMU is located in the same local power domain of its\nmaster H/W, System MMU must be initialized before it is working if\nits power domain was ever turned off. TLB invalidation according to\nunmapping on page tables must also be performed while power domain is\nturned on.\n\nThis patch ensures that resume and runtime_resume(restore_state)\nfunctions in this driver is called before the calls to resume and\nruntime_resume callback functions in the drivers of master H/Ws.\nLikewise, suspend and runtime_suspend(save_state) functions in this\ndriver is called after the calls to suspend and runtime_suspend in the\ndrivers of master H/Ws.\n\nIn order to get benefit of this support, the master H/W and its System\nMMU must resides in the same power domain in terms of Linux kernel. If\na master H/W does not use generic I/O power domain, its driver must\ncall iommu_attach_device() after its local power domain is turned on,\niommu_detach_device before turned off.\n\nSigned-off-by: Cho KyongHo \u003cpullip.cho@samsung.com\u003e\n" }, { "commit": "fe8e4fd8ee9313ed6a97461b90c3ae24f64b557e", "tree": "a6003869e0e888c9087328418887b3766725a88a", "parents": [ "8744d458591e932a32a6d82660fc4a77c744f8f6" ], "author": { "name": "Cho KyongHo", "email": "pullip.cho@samsung.com", "time": "Tue Aug 06 22:17:17 2013 +0900" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:42 2014 +0400" }, "message": "iommu/exynos: turn on useful configuration options\n\nThis turns on FLPD_CACHE, ACGEN and SYSSEL.\n\nFLPD_CACHE is a cache of 1st level page table entries that contains\nthe address of a 2nd level page table to reduce latency of page table\nwalking.\n\nACGEN is architectural clock gating that gates clocks by System MMU\nitself if it is not active. Note that ACGEN is different from clock\ngating by the CPU. ACGEN just gates clocks to the internal logic of\nSystem MMU while clock gating by the CPU gates clocks to the System\nMMU.\n\nSYSSEL selects System MMU version in some Exynos SoCs. Some Exynos\nSoCs have an option to select System MMU versions exclusively because\nthe SoCs adopts new System MMU version experimentally.\n\nThis also always selects LRU as TLB replacement policy. Selecting TLB\nreplacement policy is deprecated from System MMU 3.2. TLB in System\nMMU 3.3 has single TLB replacement policy, LRU. The bit of MMU_CFG\nselecting TLB replacement policy is remained as reserved.\n\nQoS value of page table walking is set to 15 (highst value). System\nMMU 3.3 can inherit QoS value of page table walking from its master\nH/W\u0027s transaction. This new feature is enabled by default and QoS\nvalue written to MMU_CFG is ignored.\n\nSigned-off-by: Cho KyongHo \u003cpullip.cho@samsung.com\u003e\n" }, { "commit": "8744d458591e932a32a6d82660fc4a77c744f8f6", "tree": "aea5bc0b2ded0b2ff0274ebecb80726ebecdfaaf", "parents": [ "3b2ca83194ef26ca2af2567e27605bf8b29c691b" ], "author": { "name": "Cho KyongHo", "email": "pullip.cho@samsung.com", "time": "Tue Aug 06 21:40:23 2013 +0900" }, "committer": { "name": "Andrey Konovalov", "email": "andrey.konovalov@linaro.org", "time": "Wed Apr 16 23:51:42 2014 +0400" }, "message": "iommu/exynos: remove calls to Runtime PM API functions\n\nRuntime power management by exynos-iommu driver independently from\nmaster H/W\u0027s runtime pm is not useful for power saving since attaching\nmaster H/W in probing time turns on its local power endlessly.\nThus this removes runtime pm API calls.\nRuntime PM support is added in the following commits to exynos-iommu\ndriver.\n\nSigned-off-by: Cho KyongHo \u003cpullip.cho@samsung.com\u003e\n" } ], "next": "3b2ca83194ef26ca2af2567e27605bf8b29c691b" }