tree 4660c9a1092a479dcfffb5099abe39023b376b01
parent 4c834452aad01531db949414f94f817a86348d59
author Lucas Stach <l.stach@pengutronix.de> 1405592414 +0200
committer Shawn Guo <shawn.guo@freescale.com> 1405670237 +0800

ARM: clk-imx6q: parent lvds_sel input from upstream clock gates

The i.MX6 reference manual doesn't make a clear distinction
between the fixed clock divider and the enable gate for the
pcie and sata reference clocks. This lead to the lvds mux
inputs in the imx6q clk driver to be parented from the
ref clock (which is the divider) instead of the actual gate,
which in turn prevents the upstream clock to actually be
enabled when lvds clk out is active.

This fixes a hard machine hang regression in kernel 3.16 for
boards where only pcie is active but no sata, as with this
kernel version the imx6-pcie driver is no longer enabling
the upstream clock directly but only lvds clk out.

Reported-by: Arne Ruhnau <arne.ruhnau@target-sg.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Arne Ruhnau <arne.ruhnau@target-sg.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>