tree 3cb76a5a2cbd161ce03007370f5e38c133efe21d
parent 5c92ffb1ecc7f13267cdef5dda8a838937912c93
author Matthew Wilcox <willy@linux.intel.com> 1245377759 -0700
committer Jesse Barnes <jbarnes@virtuousgeek.org> 1245449499 -0700

PCI: Fix the NIU MSI-X problem in a better way

The previous MSI-X fix (8d181018532dd709ec1f789e374cda92d7b01ce1) had
three bugs.  First, it didn't move the write that disabled the vector.
This led to writing garbage to the MSI-X vector (spotted by Michael
Ellerman).  It didn't fix the PCI resume case, and it had a race window
where the device could generate an interrupt before the MSI-X registers
were programmed (leading to a DMA to random addresses).

Fortunately, the MSI-X capability has a bit to mask all the vectors.
By setting this bit instead of clearing the enable bit, we can ensure
the device will not generate spurious interrupts.  Since the capability
is now enabled, the NIU device will not have a problem with the reads
and writes to the MSI-X registers being in the original order in the code.

Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>