| /* |
| * dts file for AppliedMicro (APM) X-Gene Storm SOC |
| * |
| * Copyright (C) 2013, Applied Micro Circuits Corporation |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| */ |
| |
| / { |
| compatible = "apm,xgene-storm"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu@000 { |
| device_type = "cpu"; |
| compatible = "apm,potenza", "arm,armv8"; |
| reg = <0x0 0x000>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@001 { |
| device_type = "cpu"; |
| compatible = "apm,potenza", "arm,armv8"; |
| reg = <0x0 0x001>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@100 { |
| device_type = "cpu"; |
| compatible = "apm,potenza", "arm,armv8"; |
| reg = <0x0 0x100>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@101 { |
| device_type = "cpu"; |
| compatible = "apm,potenza", "arm,armv8"; |
| reg = <0x0 0x101>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@200 { |
| device_type = "cpu"; |
| compatible = "apm,potenza", "arm,armv8"; |
| reg = <0x0 0x200>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@201 { |
| device_type = "cpu"; |
| compatible = "apm,potenza", "arm,armv8"; |
| reg = <0x0 0x201>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@300 { |
| device_type = "cpu"; |
| compatible = "apm,potenza", "arm,armv8"; |
| reg = <0x0 0x300>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| cpu@301 { |
| device_type = "cpu"; |
| compatible = "apm,potenza", "arm,armv8"; |
| reg = <0x0 0x301>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0x1 0x0000fff8>; |
| }; |
| }; |
| |
| gic: interrupt-controller@78010000 { |
| compatible = "arm,cortex-a15-gic"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ |
| <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ |
| <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ |
| <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ |
| interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ |
| <1 13 0xff01>, /* Non-secure Phys IRQ */ |
| <1 14 0xff01>, /* Virt IRQ */ |
| <1 15 0xff01>; /* Hyp IRQ */ |
| clock-frequency = <50000000>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| clocks { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| refclk: refclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <1>; |
| clock-frequency = <100000000>; |
| clock-output-names = "refclk"; |
| }; |
| |
| pcppll: pcppll@17000100 { |
| compatible = "apm,xgene-pcppll-clock"; |
| #clock-cells = <1>; |
| clocks = <&refclk 0>; |
| clock-names = "pcppll"; |
| reg = <0x0 0x17000100 0x0 0x1000>; |
| clock-output-names = "pcppll"; |
| type = <0>; |
| }; |
| |
| socpll: socpll@17000120 { |
| compatible = "apm,xgene-socpll-clock"; |
| #clock-cells = <1>; |
| clocks = <&refclk 0>; |
| clock-names = "socpll"; |
| reg = <0x0 0x17000120 0x0 0x1000>; |
| clock-output-names = "socpll"; |
| type = <1>; |
| }; |
| |
| socplldiv2: socplldiv2 { |
| compatible = "fixed-factor-clock"; |
| #clock-cells = <1>; |
| clocks = <&socpll 0>; |
| clock-names = "socplldiv2"; |
| clock-mult = <1>; |
| clock-div = <2>; |
| clock-output-names = "socplldiv2"; |
| }; |
| |
| qmlclk: qmlclk { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| clock-names = "qmlclk"; |
| reg = <0x0 0x1703C000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| clock-output-names = "qmlclk"; |
| }; |
| |
| ethclk: ethclk { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| clock-names = "ethclk"; |
| reg = <0x0 0x17000000 0x0 0x1000>; |
| reg-names = "div-reg"; |
| divider-offset = <0x238>; |
| divider-width = <0x9>; |
| divider-shift = <0x0>; |
| clock-output-names = "ethclk"; |
| }; |
| |
| eth8clk: eth8clk { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <ðclk 0>; |
| clock-names = "eth8clk"; |
| reg = <0x0 0x1702C000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| clock-output-names = "eth8clk"; |
| }; |
| |
| sataphy1clk: sataphy1clk@1f21c000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f21c000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| clock-output-names = "sataphy1clk"; |
| status = "disabled"; |
| csr-offset = <0x4>; |
| csr-mask = <0x00>; |
| enable-offset = <0x0>; |
| enable-mask = <0x06>; |
| }; |
| |
| sataphy2clk: sataphy1clk@1f22c000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f22c000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| clock-output-names = "sataphy2clk"; |
| status = "ok"; |
| csr-offset = <0x4>; |
| csr-mask = <0x3a>; |
| enable-offset = <0x0>; |
| enable-mask = <0x06>; |
| }; |
| |
| sataphy3clk: sataphy1clk@1f23c000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f23c000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| clock-output-names = "sataphy3clk"; |
| status = "ok"; |
| csr-offset = <0x4>; |
| csr-mask = <0x3a>; |
| enable-offset = <0x0>; |
| enable-mask = <0x06>; |
| }; |
| |
| sata01clk: sata01clk@1f21c000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f21c000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| clock-output-names = "sata01clk"; |
| csr-offset = <0x4>; |
| csr-mask = <0x05>; |
| enable-offset = <0x0>; |
| enable-mask = <0x39>; |
| }; |
| |
| sata23clk: sata23clk@1f22c000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f22c000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| clock-output-names = "sata23clk"; |
| csr-offset = <0x4>; |
| csr-mask = <0x05>; |
| enable-offset = <0x0>; |
| enable-mask = <0x39>; |
| }; |
| |
| sata45clk: sata45clk@1f23c000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x1f23c000 0x0 0x1000>; |
| reg-names = "csr-reg"; |
| clock-output-names = "sata45clk"; |
| csr-offset = <0x4>; |
| csr-mask = <0x05>; |
| enable-offset = <0x0>; |
| enable-mask = <0x39>; |
| }; |
| |
| rtcclk: rtcclk@17000000 { |
| compatible = "apm,xgene-device-clock"; |
| #clock-cells = <1>; |
| clocks = <&socplldiv2 0>; |
| reg = <0x0 0x17000000 0x0 0x2000>; |
| reg-names = "csr-reg"; |
| csr-offset = <0xc>; |
| csr-mask = <0x2>; |
| enable-offset = <0x10>; |
| enable-mask = <0x2>; |
| clock-output-names = "rtcclk"; |
| }; |
| }; |
| |
| serial0: serial@1c020000 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <0 0x1c020000 0x0 0x1000>; |
| reg-shift = <2>; |
| clock-frequency = <10000000>; /* Updated by bootloader */ |
| interrupt-parent = <&gic>; |
| interrupts = <0x0 0x4c 0x4>; |
| }; |
| |
| phy1: phy@1f21a000 { |
| compatible = "apm,xgene-phy"; |
| reg = <0x0 0x1f21a000 0x0 0x100>; |
| #phy-cells = <1>; |
| clocks = <&sataphy1clk 0>; |
| status = "disabled"; |
| apm,tx-boost-gain = <30 30 30 30 30 30>; |
| apm,tx-eye-tuning = <2 10 10 2 10 10>; |
| }; |
| |
| phy2: phy@1f22a000 { |
| compatible = "apm,xgene-phy"; |
| reg = <0x0 0x1f22a000 0x0 0x100>; |
| #phy-cells = <1>; |
| clocks = <&sataphy2clk 0>; |
| status = "ok"; |
| apm,tx-boost-gain = <30 30 30 30 30 30>; |
| apm,tx-eye-tuning = <1 10 10 2 10 10>; |
| }; |
| |
| phy3: phy@1f23a000 { |
| compatible = "apm,xgene-phy"; |
| reg = <0x0 0x1f23a000 0x0 0x100>; |
| #phy-cells = <1>; |
| clocks = <&sataphy3clk 0>; |
| status = "ok"; |
| apm,tx-boost-gain = <31 31 31 31 31 31>; |
| apm,tx-eye-tuning = <2 10 10 2 10 10>; |
| }; |
| |
| sata1: sata@1a000000 { |
| compatible = "apm,xgene-ahci"; |
| reg = <0x0 0x1a000000 0x0 0x1000>, |
| <0x0 0x1f210000 0x0 0x1000>, |
| <0x0 0x1f21d000 0x0 0x1000>, |
| <0x0 0x1f21e000 0x0 0x1000>, |
| <0x0 0x1f217000 0x0 0x1000>; |
| interrupts = <0x0 0x86 0x4>; |
| dma-coherent; |
| status = "disabled"; |
| clocks = <&sata01clk 0>; |
| phys = <&phy1 0>; |
| phy-names = "sata-phy"; |
| }; |
| |
| sata2: sata@1a400000 { |
| compatible = "apm,xgene-ahci"; |
| reg = <0x0 0x1a400000 0x0 0x1000>, |
| <0x0 0x1f220000 0x0 0x1000>, |
| <0x0 0x1f22d000 0x0 0x1000>, |
| <0x0 0x1f22e000 0x0 0x1000>, |
| <0x0 0x1f227000 0x0 0x1000>; |
| interrupts = <0x0 0x87 0x4>; |
| dma-coherent; |
| status = "ok"; |
| clocks = <&sata23clk 0>; |
| phys = <&phy2 0>; |
| phy-names = "sata-phy"; |
| }; |
| |
| sata3: sata@1a800000 { |
| compatible = "apm,xgene-ahci"; |
| reg = <0x0 0x1a800000 0x0 0x1000>, |
| <0x0 0x1f230000 0x0 0x1000>, |
| <0x0 0x1f23d000 0x0 0x1000>, |
| <0x0 0x1f23e000 0x0 0x1000>; |
| interrupts = <0x0 0x88 0x4>; |
| dma-coherent; |
| status = "ok"; |
| clocks = <&sata45clk 0>; |
| phys = <&phy3 0>; |
| phy-names = "sata-phy"; |
| }; |
| |
| rtc: rtc@10510000 { |
| compatible = "apm,xgene-rtc"; |
| reg = <0x0 0x10510000 0x0 0x400>; |
| interrupts = <0x0 0x46 0x4>; |
| #clock-cells = <1>; |
| clocks = <&rtcclk 0>; |
| }; |
| }; |
| }; |
