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Catalin Marinas4f04d8f2012-03-05 11:49:27 +00001/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_PGTABLE_HWDEF_H
17#define __ASM_PGTABLE_HWDEF_H
18
19#ifdef CONFIG_ARM64_64K_PAGES
20#include <asm/pgtable-2level-hwdef.h>
21#else
22#include <asm/pgtable-3level-hwdef.h>
23#endif
24
25/*
26 * Hardware page table definitions.
27 *
Steve Capper084bd292013-04-10 13:48:00 +010028 * Level 1 descriptor (PUD).
29 */
30
31#define PUD_TABLE_BIT (_AT(pgdval_t, 1) << 1)
Steve Capper206a2a72014-05-06 14:02:27 +010032#define PUD_TYPE_MASK (_AT(pgdval_t, 3) << 0)
33#define PUD_TYPE_SECT (_AT(pgdval_t, 1) << 0)
Steve Capper084bd292013-04-10 13:48:00 +010034
35/*
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000036 * Level 2 descriptor (PMD).
37 */
38#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
39#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
40#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
41#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
Steve Capper084bd292013-04-10 13:48:00 +010042#define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000043
44/*
45 * Section
46 */
Steve Capperaf074842013-04-19 16:23:57 +010047#define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
Steve Capperdb4ed532013-12-05 12:04:51 +000048#define PMD_SECT_PROT_NONE (_AT(pmdval_t, 1) << 58)
Steve Capperaf074842013-04-19 16:23:57 +010049#define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */
50#define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000051#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
52#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
53#define PMD_SECT_NG (_AT(pmdval_t, 1) << 11)
Catalin Marinas8e620b02012-11-15 17:21:16 +000054#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
55#define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000056
57/*
58 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
59 */
60#define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2)
61#define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2)
62
63/*
64 * Level 3 descriptor (PTE).
65 */
66#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
67#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
68#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
Steve Capper084bd292013-04-10 13:48:00 +010069#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000070#define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
71#define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
72#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
73#define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
74#define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */
Catalin Marinas8e620b02012-11-15 17:21:16 +000075#define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */
76#define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000077
78/*
79 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
80 */
81#define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2)
82#define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2)
83
84/*
Marc Zyngier36311602012-12-07 18:35:41 +000085 * 2nd stage PTE definitions
86 */
87#define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */
88#define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
89
Christoffer Dallad361f02012-11-01 17:14:45 +010090#define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
91
Marc Zyngier36311602012-12-07 18:35:41 +000092/*
93 * Memory Attribute override for Stage-2 (MemAttr[3:0])
94 */
95#define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2)
96#define PTE_S2_MEMATTR_MASK (_AT(pteval_t, 0xf) << 2)
97
98/*
99 * EL2/HYP PTE/PMD definitions
100 */
101#define PMD_HYP PMD_SECT_USER
102#define PTE_HYP PTE_USER
103
104/*
Radha Mohan Chintakuntla87366d82014-03-07 08:49:25 +0000105 * Highest possible physical address supported.
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000106 */
Radha Mohan Chintakuntla87366d82014-03-07 08:49:25 +0000107#define PHYS_MASK_SHIFT (48)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000108#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
109
110/*
111 * TCR flags.
112 */
113#define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0))
114#define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24))
115#define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24))
116#define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24))
117#define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24))
118#define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24))
119#define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26))
120#define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26))
121#define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26))
122#define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26))
123#define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26))
124#define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28))
Catalin Marinas35a86972014-04-02 17:55:40 +0100125#define TCR_TG0_4K (UL(0) << 14)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000126#define TCR_TG0_64K (UL(1) << 14)
Catalin Marinas35a86972014-04-02 17:55:40 +0100127#define TCR_TG0_16K (UL(2) << 14)
128#define TCR_TG1_16K (UL(1) << 30)
129#define TCR_TG1_4K (UL(2) << 30)
130#define TCR_TG1_64K (UL(3) << 30)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000131#define TCR_ASID16 (UL(1) << 36)
Will Deacond50240a2013-06-12 16:28:04 +0100132#define TCR_TBI0 (UL(1) << 37)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000133
134#endif