)]}'
{
  "commit": "0d258efb6a58fe047197c3b9cff8746bb176d58a",
  "tree": "8576f2af5212ec50509de1071cf7afe1ed9531a8",
  "parents": [
    "21ea28abcf825729f9698afd7357dfbf7040d4f8"
  ],
  "author": {
    "name": "Mathias Krause",
    "email": "minipli@googlemail.com",
    "time": "Sat Nov 27 16:34:46 2010 +0800"
  },
  "committer": {
    "name": "Herbert Xu",
    "email": "herbert@gondor.apana.org.au",
    "time": "Sat Nov 27 16:34:46 2010 +0800"
  },
  "message": "crypto: aesni-intel - Ported implementation to x86-32\n\nThe AES-NI instructions are also available in legacy mode so the 32-bit\narchitecture may profit from those, too.\n\nTo illustrate the performance gain here\u0027s a short summary of a dm-crypt\nspeed test on a Core i7 M620 running at 2.67GHz comparing both assembler\nimplementations:\n\nx86:                   i568       aes-ni    delta\nECB, 256 bit:     93.8 MB/s   123.3 MB/s   +31.4%\nCBC, 256 bit:     84.8 MB/s   262.3 MB/s  +209.3%\nLRW, 256 bit:    108.6 MB/s   222.1 MB/s  +104.5%\nXTS, 256 bit:    105.0 MB/s   205.5 MB/s   +95.7%\n\nAdditionally, due to some minor optimizations, the 64-bit version also\ngot a minor performance gain as seen below:\n\nx86-64:           old impl.    new impl.    delta\nECB, 256 bit:    121.1 MB/s   123.0 MB/s    +1.5%\nCBC, 256 bit:    285.3 MB/s   290.8 MB/s    +1.9%\nLRW, 256 bit:    263.7 MB/s   265.3 MB/s    +0.6%\nXTS, 256 bit:    251.1 MB/s   255.3 MB/s    +1.7%\n\nSigned-off-by: Mathias Krause \u003cminipli@googlemail.com\u003e\nReviewed-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n",
  "tree_diff": [
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      "old_path": "arch/x86/crypto/aesni-intel_asm.S",
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}