sparc32: drop sun4c support
Machines with sun4c support are very rare these days, and noone
is using them for any practical purposes.
The sun4c support has been know broken for quite some time too.
So rather than trying to keep it up-to-date, lets get rid of it.
This allows us to do some very welcome cleanup of sparc32 support.
Updated the former sun4c specifc nmi (which was also used
for sun4m UP) to be a generic UP NMI.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index f445e98..e0e0b81 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -317,8 +317,8 @@
RESTORE_ALL
.align 4
- .globl linux_trap_ipi15_sun4m
-linux_trap_ipi15_sun4m:
+ .globl linux_trap_ipi15
+linux_trap_ipi15:
SAVE_ALL
sethi %hi(0x80000000), %o2
GET_PROCESSOR4M_ID(o0)
@@ -760,20 +760,12 @@
jmp %l2 ! advance over trap instruction
rett %l2 + 0x4 ! like this...
+#ifndef CONFIG_SMP
.align 4
- .globl linux_trap_nmi_sun4c
-linux_trap_nmi_sun4c:
+ .globl linux_trap_ipi15
+linux_trap_ipi15:
SAVE_ALL
- /* Ugh, we need to clear the IRQ line. This is now
- * a very sun4c specific trap handler...
- */
- sethi %hi(interrupt_enable), %l5
- ld [%l5 + %lo(interrupt_enable)], %l5
- ldub [%l5], %l6
- andn %l6, INTS_ENAB, %l6
- stb %l6, [%l5]
-
/* Now it is safe to re-enable traps without recursion. */
or %l0, PSR_PIL, %l0
wr %l0, PSR_ET, %psr
@@ -797,6 +789,8 @@
RESTORE_ALL
+#endif /* CONFIG_SMP */
+
.align 4
.globl invalid_segment_patch1_ff
.globl invalid_segment_patch2_ff
