| /* |
| * Copyright 2015 Vishnu Patekar |
| * |
| * Vishnu Patekar <vishnupatekar0510@gmail.com> |
| * |
| * This file is dual-licensed: you can use it either under the terms |
| * of the GPL or the X11 license, at your option. Note that this dual |
| * licensing only applies to this file, and not this project as a |
| * whole. |
| * |
| * a) This file is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of the |
| * License, or (at your option) any later version. |
| * |
| * This file is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * Or, alternatively, |
| * |
| * b) Permission is hereby granted, free of charge, to any person |
| * obtaining a copy of this software and associated documentation |
| * files (the "Software"), to deal in the Software without |
| * restriction, including without limitation the rights to use, |
| * copy, modify, merge, publish, distribute, sublicense, and/or |
| * sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following |
| * conditions: |
| * |
| * The above copyright notice and this permission notice shall be |
| * included in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| #include <dt-bindings/clock/sun8i-a83t-ccu.h> |
| #include <dt-bindings/clock/sun8i-r-ccu.h> |
| #include <dt-bindings/reset/sun8i-a83t-ccu.h> |
| #include <dt-bindings/reset/sun8i-r-ccu.h> |
| |
| / { |
| interrupt-parent = <&gic>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| aliases { |
| }; |
| |
| chosen { |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <0>; |
| }; |
| |
| cpu@1 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <1>; |
| }; |
| |
| cpu@2 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <2>; |
| }; |
| |
| cpu@3 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <3>; |
| }; |
| |
| cpu@100 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <0x100>; |
| }; |
| |
| cpu@101 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <0x101>; |
| }; |
| |
| cpu@102 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <0x102>; |
| }; |
| |
| cpu@103 { |
| compatible = "arm,cortex-a7"; |
| device_type = "cpu"; |
| reg = <0x103>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| clocks { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| /* TODO: PRCM block has a mux for this. */ |
| osc24M: osc24M_clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| clock-accuracy = <50000>; |
| clock-output-names = "osc24M"; |
| }; |
| |
| /* |
| * This is called "internal OSC" in some places. |
| * It is an internal RC-based oscillator. |
| * TODO: Its controls are in the PRCM block. |
| */ |
| osc16M: osc16M_clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <16000000>; |
| clock-output-names = "osc16M"; |
| }; |
| |
| osc16Md512: osc16Md512_clk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clock-div = <512>; |
| clock-mult = <1>; |
| clocks = <&osc16M>; |
| clock-output-names = "osc16M-d512"; |
| }; |
| }; |
| |
| memory { |
| reg = <0x40000000 0x80000000>; |
| device_type = "memory"; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| syscon: syscon@1c00000 { |
| compatible = "allwinner,sun8i-a83t-system-controller", |
| "syscon"; |
| reg = <0x01c00000 0x1000>; |
| }; |
| |
| dma: dma-controller@1c02000 { |
| compatible = "allwinner,sun8i-a83t-dma"; |
| reg = <0x01c02000 0x1000>; |
| interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_DMA>; |
| resets = <&ccu RST_BUS_DMA>; |
| #dma-cells = <1>; |
| }; |
| |
| mmc0: mmc@1c0f000 { |
| compatible = "allwinner,sun8i-a83t-mmc", |
| "allwinner,sun7i-a20-mmc"; |
| reg = <0x01c0f000 0x1000>; |
| clocks = <&ccu CLK_BUS_MMC0>, |
| <&ccu CLK_MMC0>, |
| <&ccu CLK_MMC0_OUTPUT>, |
| <&ccu CLK_MMC0_SAMPLE>; |
| clock-names = "ahb", |
| "mmc", |
| "output", |
| "sample"; |
| resets = <&ccu RST_BUS_MMC0>; |
| reset-names = "ahb"; |
| interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| mmc1: mmc@1c10000 { |
| compatible = "allwinner,sun8i-a83t-mmc", |
| "allwinner,sun7i-a20-mmc"; |
| reg = <0x01c10000 0x1000>; |
| clocks = <&ccu CLK_BUS_MMC1>, |
| <&ccu CLK_MMC1>, |
| <&ccu CLK_MMC1_OUTPUT>, |
| <&ccu CLK_MMC1_SAMPLE>; |
| clock-names = "ahb", |
| "mmc", |
| "output", |
| "sample"; |
| resets = <&ccu RST_BUS_MMC1>; |
| reset-names = "ahb"; |
| interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| mmc2: mmc@1c11000 { |
| compatible = "allwinner,sun8i-a83t-emmc"; |
| reg = <0x01c11000 0x1000>; |
| clocks = <&ccu CLK_BUS_MMC2>, |
| <&ccu CLK_MMC2>, |
| <&ccu CLK_MMC2_OUTPUT>, |
| <&ccu CLK_MMC2_SAMPLE>; |
| clock-names = "ahb", |
| "mmc", |
| "output", |
| "sample"; |
| resets = <&ccu RST_BUS_MMC2>; |
| reset-names = "ahb"; |
| interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| usb_otg: usb@01c19000 { |
| compatible = "allwinner,sun8i-a83t-musb", |
| "allwinner,sun8i-a33-musb"; |
| reg = <0x01c19000 0x0400>; |
| clocks = <&ccu CLK_BUS_OTG>; |
| resets = <&ccu RST_BUS_OTG>; |
| interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "mc"; |
| phys = <&usbphy 0>; |
| phy-names = "usb"; |
| extcon = <&usbphy 0>; |
| status = "disabled"; |
| }; |
| |
| usbphy: phy@1c19400 { |
| compatible = "allwinner,sun8i-a83t-usb-phy"; |
| reg = <0x01c19400 0x10>, |
| <0x01c1a800 0x14>, |
| <0x01c1b800 0x14>; |
| reg-names = "phy_ctrl", |
| "pmu1", |
| "pmu2"; |
| clocks = <&ccu CLK_USB_PHY0>, |
| <&ccu CLK_USB_PHY1>, |
| <&ccu CLK_USB_HSIC>, |
| <&ccu CLK_USB_HSIC_12M>; |
| clock-names = "usb0_phy", |
| "usb1_phy", |
| "usb2_phy", |
| "usb2_hsic_12M"; |
| resets = <&ccu RST_USB_PHY0>, |
| <&ccu RST_USB_PHY1>, |
| <&ccu RST_USB_HSIC>; |
| reset-names = "usb0_reset", |
| "usb1_reset", |
| "usb2_reset"; |
| status = "disabled"; |
| #phy-cells = <1>; |
| }; |
| |
| ehci0: usb@1c1a000 { |
| compatible = "allwinner,sun8i-a83t-ehci", |
| "generic-ehci"; |
| reg = <0x01c1a000 0x100>; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_EHCI0>; |
| resets = <&ccu RST_BUS_EHCI0>; |
| phys = <&usbphy 1>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ohci0: usb@1c1a400 { |
| compatible = "allwinner,sun8i-a83t-ohci", |
| "generic-ohci"; |
| reg = <0x01c1a400 0x100>; |
| interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; |
| resets = <&ccu RST_BUS_OHCI0>; |
| phys = <&usbphy 1>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ehci1: usb@1c1b000 { |
| compatible = "allwinner,sun8i-a83t-ehci", |
| "generic-ehci"; |
| reg = <0x01c1b000 0x100>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_EHCI1>; |
| resets = <&ccu RST_BUS_EHCI1>; |
| phys = <&usbphy 2>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ccu: clock@1c20000 { |
| compatible = "allwinner,sun8i-a83t-ccu"; |
| reg = <0x01c20000 0x400>; |
| clocks = <&osc24M>, <&osc16Md512>; |
| clock-names = "hosc", "losc"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| pio: pinctrl@1c20800 { |
| compatible = "allwinner,sun8i-a83t-pinctrl"; |
| interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x01c20800 0x400>; |
| clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>; |
| clock-names = "apb", "hosc", "losc"; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| #gpio-cells = <3>; |
| |
| mmc0_pins: mmc0-pins { |
| pins = "PF0", "PF1", "PF2", |
| "PF3", "PF4", "PF5"; |
| function = "mmc0"; |
| drive-strength = <30>; |
| bias-pull-up; |
| }; |
| |
| mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { |
| pins = "PC5", "PC6", "PC8", "PC9", |
| "PC10", "PC11", "PC12", "PC13", |
| "PC14", "PC15", "PC16"; |
| function = "mmc2"; |
| drive-strength = <30>; |
| bias-pull-up; |
| }; |
| |
| spdif_tx_pin: spdif-tx-pin { |
| pins = "PE18"; |
| function = "spdif"; |
| }; |
| |
| uart0_pb_pins: uart0-pb-pins { |
| pins = "PB9", "PB10"; |
| function = "uart0"; |
| }; |
| |
| uart0_pf_pins: uart0-pf-pins { |
| pins = "PF2", "PF4"; |
| function = "uart0"; |
| }; |
| }; |
| |
| timer@1c20c00 { |
| compatible = "allwinner,sun4i-a10-timer"; |
| reg = <0x01c20c00 0xa0>; |
| interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&osc24M>; |
| }; |
| |
| watchdog@1c20ca0 { |
| compatible = "allwinner,sun6i-a31-wdt"; |
| reg = <0x01c20ca0 0x20>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&osc24M>; |
| }; |
| |
| spdif: spdif@1c21000 { |
| #sound-dai-cells = <0>; |
| compatible = "allwinner,sun8i-a83t-spdif", |
| "allwinner,sun8i-h3-spdif"; |
| reg = <0x01c21000 0x400>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; |
| resets = <&ccu RST_BUS_SPDIF>; |
| clock-names = "apb", "spdif"; |
| dmas = <&dma 2>; |
| dma-names = "tx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spdif_tx_pin>; |
| status = "disabled"; |
| }; |
| |
| uart0: serial@01c28000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28000 0x400>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&ccu CLK_BUS_UART0>; |
| resets = <&ccu RST_BUS_UART0>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@1c81000 { |
| compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
| reg = <0x01c81000 0x1000>, |
| <0x01c82000 0x2000>, |
| <0x01c84000 0x2000>, |
| <0x01c86000 0x2000>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| r_intc: interrupt-controller@1f00c00 { |
| compatible = "allwinner,sun8i-a83t-r-intc", |
| "allwinner,sun6i-a31-r-intc"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| reg = <0x01f00c00 0x400>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| r_ccu: clock@1f01400 { |
| compatible = "allwinner,sun8i-a83t-r-ccu"; |
| reg = <0x01f01400 0x400>; |
| clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, |
| <&ccu 6>; |
| clock-names = "hosc", "losc", "iosc", "pll-periph"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| r_pio: pinctrl@1f02c00 { |
| compatible = "allwinner,sun8i-a83t-r-pinctrl"; |
| reg = <0x01f02c00 0x400>; |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, |
| <&osc16Md512>; |
| clock-names = "apb", "hosc", "losc"; |
| gpio-controller; |
| #gpio-cells = <3>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| |
| r_rsb_pins: r-rsb-pins { |
| pins = "PL0", "PL1"; |
| function = "s_rsb"; |
| drive-strength = <20>; |
| bias-pull-up; |
| }; |
| }; |
| |
| r_rsb: rsb@1f03400 { |
| compatible = "allwinner,sun8i-a83t-rsb", |
| "allwinner,sun8i-a23-rsb"; |
| reg = <0x01f03400 0x400>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&r_ccu CLK_APB0_RSB>; |
| clock-frequency = <3000000>; |
| resets = <&r_ccu RST_APB0_RSB>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&r_rsb_pins>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| }; |
