// SPDX-License-Identifier: GPL-2.0

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			reg = <0>;
			model = "ti,c64x+";
		};
		cpu@1 {
			device_type = "cpu";
			reg = <1>;
			model = "ti,c64x+";
		};
		cpu@2 {
			device_type = "cpu";
			reg = <2>;
			model = "ti,c64x+";
		};
		cpu@3 {
			device_type = "cpu";
			reg = <3>;
			model = "ti,c64x+";
		};
		cpu@4 {
			device_type = "cpu";
			reg = <4>;
			model = "ti,c64x+";
		};
		cpu@5 {
			device_type = "cpu";
			reg = <5>;
			model = "ti,c64x+";
		};
	};

	soc {
		compatible = "simple-bus";
		model = "tms320c6472";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		core_pic: interrupt-controller {
			compatible = "ti,c64x+core-pic";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		megamod_pic: interrupt-controller@1800000 {
		       compatible = "ti,c64x+megamod-pic";
		       interrupt-controller;
		       #interrupt-cells = <1>;
		       reg = <0x1800000 0x1000>;
		       interrupt-parent = <&core_pic>;
		};

		cache-controller@1840000 {
			compatible = "ti,c64x+cache";
			reg = <0x01840000 0x8400>;
		};

		timer0: timer@25e0000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x01 >;
			reg = <0x25e0000 0x40>;
		};

		timer1: timer@25f0000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x02 >;
			reg = <0x25f0000 0x40>;
		};

		timer2: timer@2600000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x04 >;
			reg = <0x2600000 0x40>;
		};

		timer3: timer@2610000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x08 >;
			reg = <0x2610000 0x40>;
		};

		timer4: timer@2620000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x10 >;
			reg = <0x2620000 0x40>;
		};

		timer5: timer@2630000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x20 >;
			reg = <0x2630000 0x40>;
		};

		clock-controller@29a0000 {
			compatible = "ti,c6472-pll", "ti,c64x+pll";
			reg = <0x029a0000 0x200>;
			ti,c64x+pll-bypass-delay = <200>;
			ti,c64x+pll-reset-delay = <12000>;
			ti,c64x+pll-lock-delay = <80000>;
		};

		device-state-controller@2a80000 {
			compatible = "ti,c64x+dscr";
			reg = <0x02a80000 0x1000>;

			ti,dscr-devstat = <0>;
			ti,dscr-silicon-rev = <0x70c 16 0xff>;

			ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
						 0x704 5 6 0 0>;

			ti,dscr-rmii-resets = <0x208 1
					       0x20c 1>;

			ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
					       0x40c 0x420 0xbea7
					       0x41c 0x420 0xbea7>;

			ti,dscr-privperm = <0x41c 0xaaaaaaaa>;

			ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
		};
	};
};