)]}'
{
  "commit": "3c8f4ad85c4b61fcf2c56e1d281d691ac595243a",
  "tree": "f60034edaa42624c7f3d6329798e390d9654ff18",
  "parents": [
    "9ca340c98c0dc6cb60b5ebd7847302f57648f0ba"
  ],
  "author": {
    "name": "Honghui Zhang",
    "email": "honghui.zhang@mediatek.com",
    "time": "Wed Jun 08 17:50:59 2016 +0800"
  },
  "committer": {
    "name": "Joerg Roedel",
    "email": "jroedel@suse.de",
    "time": "Tue Jun 21 11:36:19 2016 +0200"
  },
  "message": "memory/mediatek: add support for mt2701\n\nMediatek SMI has two generations of HW architecture, mt8173 uses the\nsecond generation of SMI HW while mt2701 uses the first generation\nHW of SMI.\n\nThere\u0027s slight differences between the two generations, for generation 2,\nthe register which control the iommu port access PA or IOVA is at each\nlarb\u0027s register base. But for generation 1, the register is at smi ao\nbase(smi always on register base).\nBesides that, the smi async clock should be prepared and enabled for SMI\ngeneration 1 HW to transform the smi clock into emi clock domain, but is\nnot needed for SMI generation 2.\n\nThis patch add SMI driver for mt2701 which use generation 1 SMI HW.\n\nSigned-off-by: Honghui Zhang \u003chonghui.zhang@mediatek.com\u003e\nSigned-off-by: Joerg Roedel \u003cjroedel@suse.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f6b57579185afbccf4b89b8a35b276f2dbbba12f",
      "old_mode": 33188,
      "old_path": "drivers/memory/mtk-smi.c",
      "new_id": "4afbc412f95933173f04fbb02e1c1b590cb495ec",
      "new_mode": 33188,
      "new_path": "drivers/memory/mtk-smi.c"
    }
  ]
}