tree f60034edaa42624c7f3d6329798e390d9654ff18
parent 9ca340c98c0dc6cb60b5ebd7847302f57648f0ba
author Honghui Zhang <honghui.zhang@mediatek.com> 1465379459 +0800
committer Joerg Roedel <jroedel@suse.de> 1466501779 +0200

memory/mediatek: add support for mt2701

Mediatek SMI has two generations of HW architecture, mt8173 uses the
second generation of SMI HW while mt2701 uses the first generation
HW of SMI.

There's slight differences between the two generations, for generation 2,
the register which control the iommu port access PA or IOVA is at each
larb's register base. But for generation 1, the register is at smi ao
base(smi always on register base).
Besides that, the smi async clock should be prepared and enabled for SMI
generation 1 HW to transform the smi clock into emi clock domain, but is
not needed for SMI generation 2.

This patch add SMI driver for mt2701 which use generation 1 SMI HW.

Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>