/*
 * Copyright 2012 Stefan Roese
 * Stefan Roese <sr@denx.de>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"

#include <dt-bindings/thermal/thermal.h>

#include <dt-bindings/clock/sun4i-a10-pll2.h>
#include <dt-bindings/dma/sun4i-a10.h>

/ {
	interrupt-parent = <&intc>;

	aliases {
		ethernet0 = &emac;
	};

	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		framebuffer@0 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0-hdmi";
			clocks = <&ahb_gates 36>, <&ahb_gates 43>,
				 <&ahb_gates 44>, <&de_be0_clk>,
				 <&tcon0_ch1_clk>, <&dram_gates 26>;
			status = "disabled";
		};

		framebuffer@1 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
			clocks = <&ahb_gates 36>, <&ahb_gates 43>,
				 <&ahb_gates 44>, <&ahb_gates 46>,
				 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>,
				 <&dram_gates 25>, <&dram_gates 26>;
			status = "disabled";
		};

		framebuffer@2 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_fe0-de_be0-lcd0";
			clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>,
				 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,
				 <&dram_gates 25>, <&dram_gates 26>;
			status = "disabled";
		};

		framebuffer@3 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
			clocks = <&ahb_gates 34>, <&ahb_gates 36>,
				 <&ahb_gates 44>, <&ahb_gates 46>,
				 <&de_be0_clk>, <&de_fe0_clk>,
				 <&tcon0_ch1_clk>, <&dram_gates 5>,
				 <&dram_gates 25>, <&dram_gates 26>;
			status = "disabled";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
			clocks = <&cpu>;
			clock-latency = <244144>; /* 8 32k periods */
			operating-points = <
				/* kHz	  uV */
				1008000 1400000
				912000	1350000
				864000	1300000
				624000	1250000
				>;
			#cooling-cells = <2>;
			cooling-min-level = <0>;
			cooling-max-level = <3>;
		};
	};

	thermal-zones {
		cpu_thermal {
			/* milliseconds */
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&rtp>;

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				cpu_alert0: cpu_alert0 {
					/* milliCelsius */
					temperature = <850000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit {
					/* milliCelsius */
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/*
		 * This is a dummy clock, to be used as placeholder on
		 * other mux clocks when a specific parent clock is not
		 * yet implemented. It should be dropped when the driver
		 * is complete.
		 */
		dummy: dummy {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		osc24M: clk@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-osc-clk";
			reg = <0x01c20050 0x4>;
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc3M: osc3M_clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
			clocks = <&osc24M>;
			clock-output-names = "osc3M";
		};

		osc32k: clk@0 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll1: clk@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll1";
		};

		pll2: clk@01c20008 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-pll2-clk";
			reg = <0x01c20008 0x8>;
			clocks = <&osc24M>;
			clock-output-names = "pll2-1x", "pll2-2x",
					     "pll2-4x", "pll2-8x";
		};

		pll3: clk@01c20010 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll3-clk";
			reg = <0x01c20010 0x4>;
			clocks = <&osc3M>;
			clock-output-names = "pll3";
		};

		pll3x2: pll3x2_clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <1>;
			clock-mult = <2>;
			clocks = <&pll3>;
			clock-output-names = "pll3-2x";
		};

		pll4: clk@01c20018 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll1-clk";
			reg = <0x01c20018 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll4";
		};

		pll5: clk@01c20020 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-pll5-clk";
			reg = <0x01c20020 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll5_ddr", "pll5_other";
		};

		pll6: clk@01c20028 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6_sata", "pll6_other", "pll6";
		};

		pll7: clk@01c20030 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll3-clk";
			reg = <0x01c20030 0x4>;
			clocks = <&osc3M>;
			clock-output-names = "pll7";
		};

		pll7x2: pll7x2_clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <1>;
			clock-mult = <2>;
			clocks = <&pll7>;
			clock-output-names = "pll7-2x";
		};

		/* dummy is 200M */
		cpu: cpu@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-cpu-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
			clock-output-names = "cpu";
		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-axi-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
			clock-output-names = "axi";
		};

		axi_gates: clk@01c2005c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-axi-gates-clk";
			reg = <0x01c2005c 0x4>;
			clocks = <&axi>;
			clock-indices = <0>;
			clock-output-names = "axi_dram";
		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&axi>;
			clock-output-names = "ahb";
		};

		ahb_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
			clock-indices = <0>, <1>,
					<2>, <3>,
					<4>, <5>, <6>,
					<7>, <8>, <9>,
					<10>, <11>, <12>,
					<13>, <14>, <16>,
					<17>, <18>, <20>,
					<21>, <22>, <23>,
					<24>, <25>, <26>,
					<32>, <33>, <34>,
					<35>, <36>, <37>,
					<40>, <41>, <43>,
					<44>, <45>,
					<46>, <47>,
					<50>, <52>;
			clock-output-names = "ahb_usb0", "ahb_ehci0",
					     "ahb_ohci0", "ahb_ehci1",
					     "ahb_ohci1", "ahb_ss", "ahb_dma",
					     "ahb_bist", "ahb_mmc0", "ahb_mmc1",
					     "ahb_mmc2", "ahb_mmc3", "ahb_ms",
					     "ahb_nand", "ahb_sdram", "ahb_ace",
					     "ahb_emac", "ahb_ts", "ahb_spi0",
					     "ahb_spi1", "ahb_spi2", "ahb_spi3",
					     "ahb_pata", "ahb_sata", "ahb_gps",
					     "ahb_ve", "ahb_tvd", "ahb_tve0",
					     "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
					     "ahb_csi0", "ahb_csi1", "ahb_hdmi",
					     "ahb_de_be0", "ahb_de_be1",
					     "ahb_de_fe0", "ahb_de_fe1",
					     "ahb_mp", "ahb_mali400";
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
			clock-output-names = "apb0";
		};

		apb0_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
			clock-indices = <0>, <1>,
					<2>, <3>,
					<5>, <6>,
					<7>, <10>;
			clock-output-names = "apb0_codec", "apb0_spdif",
					     "apb0_ac97", "apb0_iis",
					     "apb0_pio", "apb0_ir0",
					     "apb0_ir1", "apb0_keypad";
		};

		apb1: clk@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
			clock-output-names = "apb1";
		};

		apb1_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
			clock-indices = <0>, <1>,
					<2>, <4>,
					<5>, <6>,
					<7>, <16>,
					<17>, <18>,
					<19>, <20>,
					<21>, <22>,
					<23>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
					     "apb1_i2c2", "apb1_can",
					     "apb1_scr", "apb1_ps20",
					     "apb1_ps21", "apb1_uart0",
					     "apb1_uart1", "apb1_uart2",
					     "apb1_uart3", "apb1_uart4",
					     "apb1_uart5", "apb1_uart6",
					     "apb1_uart7";
		};

		nand_clk: clk@01c20080 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20080 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "nand";
		};

		ms_clk: clk@01c20084 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20084 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ms";
		};

		mmc0_clk: clk@01c20088 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc0",
					     "mmc0_output",
					     "mmc0_sample";
		};

		mmc1_clk: clk@01c2008c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc1",
					     "mmc1_output",
					     "mmc1_sample";
		};

		mmc2_clk: clk@01c20090 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc2",
					     "mmc2_output",
					     "mmc2_sample";
		};

		mmc3_clk: clk@01c20094 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20094 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc3",
					     "mmc3_output",
					     "mmc3_sample";
		};

		ts_clk: clk@01c20098 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20098 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ts";
		};

		ss_clk: clk@01c2009c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c2009c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ss";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi2";
		};

		pata_clk: clk@01c200ac {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200ac 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "pata";
		};

		ir0_clk: clk@01c200b0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200b0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir0";
		};

		ir1_clk: clk@01c200b4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200b4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir1";
		};

		spdif_clk: clk@01c200c0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod1-clk";
			reg = <0x01c200c0 0x4>;
			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
				 <&pll2 SUN4I_A10_PLL2_4X>,
				 <&pll2 SUN4I_A10_PLL2_2X>,
				 <&pll2 SUN4I_A10_PLL2_1X>;
			clock-output-names = "spdif";
		};

		usb_clk: clk@01c200cc {
			#clock-cells = <1>;
			#reset-cells = <1>;
			compatible = "allwinner,sun4i-a10-usb-clk";
			reg = <0x01c200cc 0x4>;
			clocks = <&pll6 1>;
			clock-output-names = "usb_ohci0", "usb_ohci1",
					     "usb_phy";
		};

		spi3_clk: clk@01c200d4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200d4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi3";
		};

		dram_gates: clk@01c20100 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-dram-gates-clk";
			reg = <0x01c20100 0x4>;
			clocks = <&pll5 0>;
			clock-indices = <0>,
					<1>, <2>,
					<3>,
					<4>,
					<5>, <6>,
					<15>,
					<24>, <25>,
					<26>, <27>,
					<28>, <29>;
			clock-output-names = "dram_ve",
					     "dram_csi0", "dram_csi1",
					     "dram_ts",
					     "dram_tvd",
					     "dram_tve0", "dram_tve1",
					     "dram_output",
					     "dram_de_fe1", "dram_de_fe0",
					     "dram_de_be0", "dram_de_be1",
					     "dram_de_mp", "dram_ace";
		};

		de_be0_clk: clk@01c20104 {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-display-clk";
			reg = <0x01c20104 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll5 1>;
			clock-output-names = "de-be0";
		};

		de_be1_clk: clk@01c20108 {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-display-clk";
			reg = <0x01c20108 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll5 1>;
			clock-output-names = "de-be1";
		};

		de_fe0_clk: clk@01c2010c {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-display-clk";
			reg = <0x01c2010c 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll5 1>;
			clock-output-names = "de-fe0";
		};

		de_fe1_clk: clk@01c20110 {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-display-clk";
			reg = <0x01c20110 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll5 1>;
			clock-output-names = "de-fe1";
		};


		tcon0_ch0_clk: clk@01c20118 {
			#clock-cells = <0>;
			#reset-cells = <1>;
			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
			reg = <0x01c20118 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
			clock-output-names = "tcon0-ch0-sclk";

		};

		tcon1_ch0_clk: clk@01c2011c {
			#clock-cells = <0>;
			#reset-cells = <1>;
			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
			reg = <0x01c2011c 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
			clock-output-names = "tcon1-ch0-sclk";

		};

		tcon0_ch1_clk: clk@01c2012c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
			reg = <0x01c2012c 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
			clock-output-names = "tcon0-ch1-sclk";

		};

		tcon1_ch1_clk: clk@01c20130 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
			reg = <0x01c20130 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
			clock-output-names = "tcon1-ch1-sclk";

		};

		ve_clk: clk@01c2013c {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-ve-clk";
			reg = <0x01c2013c 0x4>;
			clocks = <&pll4>;
			clock-output-names = "ve";
		};

		codec_clk: clk@01c20140 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-codec-clk";
			reg = <0x01c20140 0x4>;
			clocks = <&pll2 SUN4I_A10_PLL2_1X>;
			clock-output-names = "codec";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		sram-controller@01c00000 {
			compatible = "allwinner,sun4i-a10-sram-controller";
			reg = <0x01c00000 0x30>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			sram_a: sram@00000000 {
				compatible = "mmio-sram";
				reg = <0x00000000 0xc000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00000000 0xc000>;

				emac_sram: sram-section@8000 {
					compatible = "allwinner,sun4i-a10-sram-a3-a4";
					reg = <0x8000 0x4000>;
					status = "disabled";
				};
			};

			sram_d: sram@00010000 {
				compatible = "mmio-sram";
				reg = <0x00010000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00010000 0x1000>;

				otg_sram: sram-section@0000 {
					compatible = "allwinner,sun4i-a10-sram-d";
					reg = <0x0000 0x1000>;
					status = "disabled";
				};
			};
		};

		dma: dma-controller@01c02000 {
			compatible = "allwinner,sun4i-a10-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <27>;
			clocks = <&ahb_gates 6>;
			#dma-cells = <2>;
		};

		nfc: nand@01c03000 {
			compatible = "allwinner,sun4i-a10-nand";
			reg = <0x01c03000 0x1000>;
			interrupts = <37>;
			clocks = <&ahb_gates 13>, <&nand_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 3>;
			dma-names = "rxtx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi0: spi@01c05000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c05000 0x1000>;
			interrupts = <10>;
			clocks = <&ahb_gates 20>, <&spi0_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
			       <&dma SUN4I_DMA_DEDICATED 26>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@01c06000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c06000 0x1000>;
			interrupts = <11>;
			clocks = <&ahb_gates 21>, <&spi1_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
			       <&dma SUN4I_DMA_DEDICATED 8>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		emac: ethernet@01c0b000 {
			compatible = "allwinner,sun4i-a10-emac";
			reg = <0x01c0b000 0x1000>;
			interrupts = <55>;
			clocks = <&ahb_gates 17>;
			allwinner,sram = <&emac_sram 1>;
			status = "disabled";
		};

		mdio: mdio@01c0b080 {
			compatible = "allwinner,sun4i-a10-mdio";
			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc0: mmc@01c0f000 {
			compatible = "allwinner,sun4i-a10-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ahb_gates 8>,
				 <&mmc0_clk 0>,
				 <&mmc0_clk 1>,
				 <&mmc0_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			interrupts = <32>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@01c10000 {
			compatible = "allwinner,sun4i-a10-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ahb_gates 9>,
				 <&mmc1_clk 0>,
				 <&mmc1_clk 1>,
				 <&mmc1_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			interrupts = <33>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@01c11000 {
			compatible = "allwinner,sun4i-a10-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ahb_gates 10>,
				 <&mmc2_clk 0>,
				 <&mmc2_clk 1>,
				 <&mmc2_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			interrupts = <34>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc3: mmc@01c12000 {
			compatible = "allwinner,sun4i-a10-mmc";
			reg = <0x01c12000 0x1000>;
			clocks = <&ahb_gates 11>,
				 <&mmc3_clk 0>,
				 <&mmc3_clk 1>,
				 <&mmc3_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			interrupts = <35>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		usb_otg: usb@01c13000 {
			compatible = "allwinner,sun4i-a10-musb";
			reg = <0x01c13000 0x0400>;
			clocks = <&ahb_gates 0>;
			interrupts = <38>;
			interrupt-names = "mc";
			phys = <&usbphy 0>;
			phy-names = "usb";
			extcon = <&usbphy 0>;
			allwinner,sram = <&otg_sram 1>;
			status = "disabled";
		};

		usbphy: phy@01c13400 {
			#phy-cells = <1>;
			compatible = "allwinner,sun4i-a10-usb-phy";
			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
			reg-names = "phy_ctrl", "pmu1", "pmu2";
			clocks = <&usb_clk 8>;
			clock-names = "usb_phy";
			resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
			reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
			status = "disabled";
		};

		ehci0: usb@01c14000 {
			compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
			reg = <0x01c14000 0x100>;
			interrupts = <39>;
			clocks = <&ahb_gates 1>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci0: usb@01c14400 {
			compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
			reg = <0x01c14400 0x100>;
			interrupts = <64>;
			clocks = <&usb_clk 6>, <&ahb_gates 2>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		crypto: crypto-engine@01c15000 {
			compatible = "allwinner,sun4i-a10-crypto";
			reg = <0x01c15000 0x1000>;
			interrupts = <86>;
			clocks = <&ahb_gates 5>, <&ss_clk>;
			clock-names = "ahb", "mod";
		};

		spi2: spi@01c17000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c17000 0x1000>;
			interrupts = <12>;
			clocks = <&ahb_gates 22>, <&spi2_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
			       <&dma SUN4I_DMA_DEDICATED 28>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		ahci: sata@01c18000 {
			compatible = "allwinner,sun4i-a10-ahci";
			reg = <0x01c18000 0x1000>;
			interrupts = <56>;
			clocks = <&pll6 0>, <&ahb_gates 25>;
			status = "disabled";
		};

		ehci1: usb@01c1c000 {
			compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
			reg = <0x01c1c000 0x100>;
			interrupts = <40>;
			clocks = <&ahb_gates 3>;
			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci1: usb@01c1c400 {
			compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
			reg = <0x01c1c400 0x100>;
			interrupts = <65>;
			clocks = <&usb_clk 7>, <&ahb_gates 4>;
			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

		spi3: spi@01c1f000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c1f000 0x1000>;
			interrupts = <50>;
			clocks = <&ahb_gates 23>, <&spi3_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 31>,
			       <&dma SUN4I_DMA_DEDICATED 30>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		intc: interrupt-controller@01c20400 {
			compatible = "allwinner,sun4i-a10-ic";
			reg = <0x01c20400 0x400>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun4i-a10-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <28>;
			clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#gpio-cells = <3>;

			can0_pins_a: can0@0 {
				pins = "PH20", "PH21";
				function = "can";
			};

			emac_pins_a: emac0@0 {
				pins = "PA0", "PA1", "PA2",
				       "PA3", "PA4", "PA5", "PA6",
				       "PA7", "PA8", "PA9", "PA10",
				       "PA11", "PA12", "PA13", "PA14",
				       "PA15", "PA16";
				function = "emac";
			};

			i2c0_pins_a: i2c0@0 {
				pins = "PB0", "PB1";
				function = "i2c0";
			};

			i2c1_pins_a: i2c1@0 {
				pins = "PB18", "PB19";
				function = "i2c1";
			};

			i2c2_pins_a: i2c2@0 {
				pins = "PB20", "PB21";
				function = "i2c2";
			};

			ir0_rx_pins_a: ir0@0 {
				pins = "PB4";
				function = "ir0";
			};

			ir0_tx_pins_a: ir0@1 {
				pins = "PB3";
				function = "ir0";
			};

			ir1_rx_pins_a: ir1@0 {
				pins = "PB23";
				function = "ir1";
			};

			ir1_tx_pins_a: ir1@1 {
				pins = "PB22";
				function = "ir1";
			};

			mmc0_pins_a: mmc0@0 {
				pins = "PF0", "PF1", "PF2",
				       "PF3", "PF4", "PF5";
				function = "mmc0";
				drive-strength = <30>;
				bias-pull-up;
			};

			ps20_pins_a: ps20@0 {
				pins = "PI20", "PI21";
				function = "ps2";
			};

			ps21_pins_a: ps21@0 {
				pins = "PH12", "PH13";
				function = "ps2";
			};

			pwm0_pins_a: pwm0@0 {
				pins = "PB2";
				function = "pwm";
			};

			pwm1_pins_a: pwm1@0 {
				pins = "PI3";
				function = "pwm";
			};

			spdif_tx_pins_a: spdif@0 {
				pins = "PB13";
				function = "spdif";
				bias-pull-up;
			};

			spi0_pins_a: spi0@0 {
				pins = "PI11", "PI12", "PI13";
				function = "spi0";
			};

			spi0_cs0_pins_a: spi0_cs0@0 {
				pins = "PI10";
				function = "spi0";
			};

			spi1_pins_a: spi1@0 {
				pins = "PI17", "PI18", "PI19";
				function = "spi1";
			};

			spi1_cs0_pins_a: spi1_cs0@0 {
				pins = "PI16";
				function = "spi1";
			};

			spi2_pins_a: spi2@0 {
				pins = "PC20", "PC21", "PC22";
				function = "spi2";
			};

			spi2_pins_b: spi2@1 {
				pins = "PB15", "PB16", "PB17";
				function = "spi2";
			};

			spi2_cs0_pins_a: spi2_cs0@0 {
				pins = "PC19";
				function = "spi2";
			};

			spi2_cs0_pins_b: spi2_cs0@1 {
				pins = "PB14";
				function = "spi2";
			};

			uart0_pins_a: uart0@0 {
				pins = "PB22", "PB23";
				function = "uart0";
			};

			uart0_pins_b: uart0@1 {
				pins = "PF2", "PF4";
				function = "uart0";
			};

			uart1_pins_a: uart1@0 {
				pins = "PA10", "PA11";
				function = "uart1";
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <22>;
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
			compatible = "allwinner,sun4i-a10-wdt";
			reg = <0x01c20c90 0x10>;
		};

		rtc: rtc@01c20d00 {
			compatible = "allwinner,sun4i-a10-rtc";
			reg = <0x01c20d00 0x20>;
			interrupts = <24>;
		};

		pwm: pwm@01c20e00 {
			compatible = "allwinner,sun4i-a10-pwm";
			reg = <0x01c20e00 0xc>;
			clocks = <&osc24M>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		spdif: spdif@01c21000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun4i-a10-spdif";
			reg = <0x01c21000 0x400>;
			interrupts = <13>;
			clocks = <&apb0_gates 1>, <&spdif_clk>;
			clock-names = "apb", "spdif";
			dmas = <&dma SUN4I_DMA_NORMAL 2>,
			       <&dma SUN4I_DMA_NORMAL 2>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		ir0: ir@01c21800 {
			compatible = "allwinner,sun4i-a10-ir";
			clocks = <&apb0_gates 6>, <&ir0_clk>;
			clock-names = "apb", "ir";
			interrupts = <5>;
			reg = <0x01c21800 0x40>;
			status = "disabled";
		};

		ir1: ir@01c21c00 {
			compatible = "allwinner,sun4i-a10-ir";
			clocks = <&apb0_gates 7>, <&ir1_clk>;
			clock-names = "apb", "ir";
			interrupts = <6>;
			reg = <0x01c21c00 0x40>;
			status = "disabled";
		};

		lradc: lradc@01c22800 {
			compatible = "allwinner,sun4i-a10-lradc-keys";
			reg = <0x01c22800 0x100>;
			interrupts = <31>;
			status = "disabled";
		};

		codec: codec@01c22c00 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun4i-a10-codec";
			reg = <0x01c22c00 0x40>;
			interrupts = <30>;
			clocks = <&apb0_gates 0>, <&codec_clk>;
			clock-names = "apb", "codec";
			dmas = <&dma SUN4I_DMA_NORMAL 19>,
			       <&dma SUN4I_DMA_NORMAL 19>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		sid: eeprom@01c23800 {
			compatible = "allwinner,sun4i-a10-sid";
			reg = <0x01c23800 0x10>;
		};

		rtp: rtp@01c25000 {
			compatible = "allwinner,sun4i-a10-ts";
			reg = <0x01c25000 0x100>;
			interrupts = <29>;
			#thermal-sensor-cells = <0>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <2>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <3>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <17>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <18>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 21>;
			status = "disabled";
		};

		uart6: serial@01c29800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29800 0x400>;
			interrupts = <19>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 22>;
			status = "disabled";
		};

		uart7: serial@01c29c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29c00 0x400>;
			interrupts = <20>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 23>;
			status = "disabled";
		};

		ps20: ps2@01c2a000 {
			compatible = "allwinner,sun4i-a10-ps2";
			reg = <0x01c2a000 0x400>;
			interrupts = <62>;
			clocks = <&apb1_gates 6>;
			status = "disabled";
		};

		ps21: ps2@01c2a400 {
			compatible = "allwinner,sun4i-a10-ps2";
			reg = <0x01c2a400 0x400>;
			interrupts = <63>;
			clocks = <&apb1_gates 7>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <7>;
			clocks = <&apb1_gates 0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <8>;
			clocks = <&apb1_gates 1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <9>;
			clocks = <&apb1_gates 2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		can0: can@01c2bc00 {
			compatible = "allwinner,sun4i-a10-can";
			reg = <0x01c2bc00 0x400>;
			interrupts = <26>;
			clocks = <&apb1_gates 4>;
			status = "disabled";
		};
	};
};