tree 003feaff3289f9d27292d2332710e951f142ea25
parent 8364f5d96509e206f02a74bbdc2d4e3742cdefe4
author Laxman Dewangan <ldewangan@nvidia.com> 1360682279 +0530
committer Stephen Warren <swarren@nvidia.com> 1360779423 -0700

clk: tegra: initialise parent of uart clocks

Initialise the parent of UARTs to PLLP and disabling clock by
default.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>