blob: d74bca76e2614689186eed3cc4368d40c739cd20 [file] [log] [blame]
/*
* DCE_11_0 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef DCE_11_0_ENUM_H
#define DCE_11_0_ENUM_H
typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0,
CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
} CRTC_CONTROL_CRTC_START_POINT_CNTL;
typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0,
CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0,
CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2,
CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0,
CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1,
} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0,
CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1,
} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x0,
CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x1,
} CRTC_CONTROL_CRTC_SOF_PULL_EN;
typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x0,
CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x1,
} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x0,
CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x1,
} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x0,
CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x1,
} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1,
} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0,
CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1,
} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0,
CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1,
} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK {
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe,
CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf,
} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK;
typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0,
CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1,
} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0,
CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1,
} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x0,
CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x1,
} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x0,
CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x1,
} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x7,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x8,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x9,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0xa,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0xb,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0xc,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VIDEO = 0xf,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x10,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x11,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x12,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x13,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16,
CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17,
} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1,
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2,
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3,
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4,
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5,
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6,
CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7,
} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0,
CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1,
} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x0,
CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x1,
} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x7,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x8,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x9,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0xa,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0xb,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0xc,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VIDEO = 0xf,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x10,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x11,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x12,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x13,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16,
CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17,
} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1,
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2,
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3,
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4,
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5,
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6,
CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7,
} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0,
CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1,
} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x0,
CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x1,
} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0,
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1,
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2,
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3,
} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0,
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1,
} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0,
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1,
} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0,
CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1,
} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GPIO= 0x10,
} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1,
} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0,
CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1,
} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0,
CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1,
CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2,
CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3,
} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x0,
CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x1,
} CRTC_CONTROL_CRTC_MASTER_EN;
typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x0,
CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x1,
} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x0,
CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x1,
} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0,
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1,
} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0,
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1,
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2,
CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3,
} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0,
CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1,
} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0,
CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1,
} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x0,
CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x1,
} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0,
CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1,
} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0,
CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1,
} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0,
CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1,
CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2,
CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3,
} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0,
CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1,
} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0,
CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1,
} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0,
CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1,
} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x0,
CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x1,
} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x0,
CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x1,
} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0,
CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1,
CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2,
CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3,
} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0,
CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1,
} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0,
CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1,
} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0,
CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1,
} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x0,
CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x1,
} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0,
CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x0,
CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x1,
} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0,
CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1,
} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0,
CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1,
} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0,
CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1,
} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1,
} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7,
} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1,
} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2,
CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3,
} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x0,
MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x1,
} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0,
MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1,
} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x0,
MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x1,
} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x0,
MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x1,
MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x2,
MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x3,
} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0,
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1,
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2,
MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3,
} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0,
CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1,
CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2,
} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x0,
CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x1,
} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0,
CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1,
} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0,
CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1,
} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0,
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0,
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0,
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0,
CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0,
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0,
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0,
CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0,
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0,
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0,
CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x0,
CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x1,
} CRTC_CRC_CNTL_CRTC_CRC_EN;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x0,
CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x1,
} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x0,
CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x1,
CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x2,
CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x3,
} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x0,
CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x1,
CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2,
CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3,
} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0,
CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1,
} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x0,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x1,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x2,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x3,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x4,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x5,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x6,
CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x7,
} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x0,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x1,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x2,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x3,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x4,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x5,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x6,
CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x7,
} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0,
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1,
} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0,
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1,
} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0,
CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1,
} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0,
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1,
} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0,
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1,
} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0,
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1,
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2,
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3,
} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0,
CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1,
} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
typedef enum CRTC_V_SYNC_A_POL {
CRTC_V_SYNC_A_POL_HIGH = 0x0,
CRTC_V_SYNC_A_POL_LOW = 0x1,
} CRTC_V_SYNC_A_POL;
typedef enum CRTC_H_SYNC_A_POL {
CRTC_H_SYNC_A_POL_HIGH = 0x0,
CRTC_H_SYNC_A_POL_LOW = 0x1,
} CRTC_H_SYNC_A_POL;
typedef enum CRTC_HORZ_REPETITION_COUNT {
CRTC_HORZ_REPETITION_COUNT_0 = 0x0,
CRTC_HORZ_REPETITION_COUNT_1 = 0x1,
CRTC_HORZ_REPETITION_COUNT_2 = 0x2,
CRTC_HORZ_REPETITION_COUNT_3 = 0x3,
CRTC_HORZ_REPETITION_COUNT_4 = 0x4,
CRTC_HORZ_REPETITION_COUNT_5 = 0x5,
CRTC_HORZ_REPETITION_COUNT_6 = 0x6,
CRTC_HORZ_REPETITION_COUNT_7 = 0x7,
CRTC_HORZ_REPETITION_COUNT_8 = 0x8,
CRTC_HORZ_REPETITION_COUNT_9 = 0x9,
CRTC_HORZ_REPETITION_COUNT_10 = 0xa,
CRTC_HORZ_REPETITION_COUNT_11 = 0xb,
CRTC_HORZ_REPETITION_COUNT_12 = 0xc,
CRTC_HORZ_REPETITION_COUNT_13 = 0xd,
CRTC_HORZ_REPETITION_COUNT_14 = 0xe,
CRTC_HORZ_REPETITION_COUNT_15 = 0xf,
} CRTC_HORZ_REPETITION_COUNT;
typedef enum PERFCOUNTER_CVALUE_SEL {
PERFCOUNTER_CVALUE_SEL_47_0 = 0x0,
PERFCOUNTER_CVALUE_SEL_15_0 = 0x1,
PERFCOUNTER_CVALUE_SEL_31_16 = 0x2,
PERFCOUNTER_CVALUE_SEL_47_32 = 0x3,
PERFCOUNTER_CVALUE_SEL_11_0 = 0x4,
PERFCOUNTER_CVALUE_SEL_23_12 = 0x5,
PERFCOUNTER_CVALUE_SEL_35_24 = 0x6,
PERFCOUNTER_CVALUE_SEL_47_36 = 0x7,
} PERFCOUNTER_CVALUE_SEL;
typedef enum PERFCOUNTER_INC_MODE {
PERFCOUNTER_INC_MODE_MULTI_BIT = 0x0,
PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x1,
PERFCOUNTER_INC_MODE_LSB = 0x2,
PERFCOUNTER_INC_MODE_POS_EDGE = 0x3,
} PERFCOUNTER_INC_MODE;
typedef enum PERFCOUNTER_HW_CNTL_SEL {
PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x0,
PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x1,
} PERFCOUNTER_HW_CNTL_SEL;
typedef enum PERFCOUNTER_RUNEN_MODE {
PERFCOUNTER_RUNEN_MODE_LEVEL = 0x0,
PERFCOUNTER_RUNEN_MODE_EDGE = 0x1,
} PERFCOUNTER_RUNEN_MODE;
typedef enum PERFCOUNTER_CNTOFF_START_DIS {
PERFCOUNTER_CNTOFF_START_ENABLE = 0x0,
PERFCOUNTER_CNTOFF_START_DISABLE = 0x1,
} PERFCOUNTER_CNTOFF_START_DIS;
typedef enum PERFCOUNTER_RESTART_EN {
PERFCOUNTER_RESTART_DISABLE = 0x0,
PERFCOUNTER_RESTART_ENABLE = 0x1,
} PERFCOUNTER_RESTART_EN;
typedef enum PERFCOUNTER_INT_EN {
PERFCOUNTER_INT_DISABLE = 0x0,
PERFCOUNTER_INT_ENABLE = 0x1,
} PERFCOUNTER_INT_EN;
typedef enum PERFCOUNTER_OFF_MASK {
PERFCOUNTER_OFF_MASK_DISABLE = 0x0,
PERFCOUNTER_OFF_MASK_ENABLE = 0x1,
} PERFCOUNTER_OFF_MASK;
typedef enum PERFCOUNTER_ACTIVE {
PERFCOUNTER_IS_IDLE = 0x0,
PERFCOUNTER_IS_ACTIVE = 0x1,
} PERFCOUNTER_ACTIVE;
typedef enum PERFCOUNTER_INT_TYPE {
PERFCOUNTER_INT_TYPE_LEVEL = 0x0,
PERFCOUNTER_INT_TYPE_PULSE = 0x1,
} PERFCOUNTER_INT_TYPE;
typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x0,
PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x1,
} PERFCOUNTER_COUNTED_VALUE_TYPE;
typedef enum PERFCOUNTER_CNTL_SEL {
PERFCOUNTER_CNTL_SEL_0 = 0x0,
PERFCOUNTER_CNTL_SEL_1 = 0x1,
PERFCOUNTER_CNTL_SEL_2 = 0x2,
PERFCOUNTER_CNTL_SEL_3 = 0x3,
PERFCOUNTER_CNTL_SEL_4 = 0x4,
PERFCOUNTER_CNTL_SEL_5 = 0x5,
PERFCOUNTER_CNTL_SEL_6 = 0x6,
PERFCOUNTER_CNTL_SEL_7 = 0x7,
} PERFCOUNTER_CNTL_SEL;
typedef enum PERFCOUNTER_CNT0_STATE {
PERFCOUNTER_CNT0_STATE_RESET = 0x0,
PERFCOUNTER_CNT0_STATE_START = 0x1,
PERFCOUNTER_CNT0_STATE_FREEZE = 0x2,
PERFCOUNTER_CNT0_STATE_HW = 0x3,
} PERFCOUNTER_CNT0_STATE;
typedef enum PERFCOUNTER_STATE_SEL0 {
PERFCOUNTER_STATE_SEL0_GLOBAL = 0x0,
PERFCOUNTER_STATE_SEL0_LOCAL = 0x1,
} PERFCOUNTER_STATE_SEL0;
typedef enum PERFCOUNTER_CNT1_STATE {
PERFCOUNTER_CNT1_STATE_RESET = 0x0,
PERFCOUNTER_CNT1_STATE_START = 0x1,
PERFCOUNTER_CNT1_STATE_FREEZE = 0x2,
PERFCOUNTER_CNT1_STATE_HW = 0x3,
} PERFCOUNTER_CNT1_STATE;
typedef enum PERFCOUNTER_STATE_SEL1 {
PERFCOUNTER_STATE_SEL1_GLOBAL = 0x0,
PERFCOUNTER_STATE_SEL1_LOCAL = 0x1,
} PERFCOUNTER_STATE_SEL1;
typedef enum PERFCOUNTER_CNT2_STATE {
PERFCOUNTER_CNT2_STATE_RESET = 0x0,
PERFCOUNTER_CNT2_STATE_START = 0x1,
PERFCOUNTER_CNT2_STATE_FREEZE = 0x2,
PERFCOUNTER_CNT2_STATE_HW = 0x3,
} PERFCOUNTER_CNT2_STATE;
typedef enum PERFCOUNTER_STATE_SEL2 {
PERFCOUNTER_STATE_SEL2_GLOBAL = 0x0,
PERFCOUNTER_STATE_SEL2_LOCAL = 0x1,
} PERFCOUNTER_STATE_SEL2;
typedef enum PERFCOUNTER_CNT3_STATE {
PERFCOUNTER_CNT3_STATE_RESET = 0x0,
PERFCOUNTER_CNT3_STATE_START = 0x1,
PERFCOUNTER_CNT3_STATE_FREEZE = 0x2,
PERFCOUNTER_CNT3_STATE_HW = 0x3,
} PERFCOUNTER_CNT3_STATE;
typedef enum PERFCOUNTER_STATE_SEL3 {
PERFCOUNTER_STATE_SEL3_GLOBAL = 0x0,
PERFCOUNTER_STATE_SEL3_LOCAL = 0x1,
} PERFCOUNTER_STATE_SEL3;
typedef enum PERFCOUNTER_CNT4_STATE {
PERFCOUNTER_CNT4_STATE_RESET = 0x0,
PERFCOUNTER_CNT4_STATE_START = 0x1,
PERFCOUNTER_CNT4_STATE_FREEZE = 0x2,
PERFCOUNTER_CNT4_STATE_HW = 0x3,
} PERFCOUNTER_CNT4_STATE;
typedef enum PERFCOUNTER_STATE_SEL4 {
PERFCOUNTER_STATE_SEL4_GLOBAL = 0x0,
PERFCOUNTER_STATE_SEL4_LOCAL = 0x1,
} PERFCOUNTER_STATE_SEL4;
typedef enum PERFCOUNTER_CNT5_STATE {
PERFCOUNTER_CNT5_STATE_RESET = 0x0,
PERFCOUNTER_CNT5_STATE_START = 0x1,
PERFCOUNTER_CNT5_STATE_FREEZE = 0x2,
PERFCOUNTER_CNT5_STATE_HW = 0x3,
} PERFCOUNTER_CNT5_STATE;
typedef enum PERFCOUNTER_STATE_SEL5 {
PERFCOUNTER_STATE_SEL5_GLOBAL = 0x0,
PERFCOUNTER_STATE_SEL5_LOCAL = 0x1,
} PERFCOUNTER_STATE_SEL5;
typedef enum PERFCOUNTER_CNT6_STATE {
PERFCOUNTER_CNT6_STATE_RESET = 0x0,
PERFCOUNTER_CNT6_STATE_START = 0x1,
PERFCOUNTER_CNT6_STATE_FREEZE = 0x2,
PERFCOUNTER_CNT6_STATE_HW = 0x3,
} PERFCOUNTER_CNT6_STATE;
typedef enum PERFCOUNTER_STATE_SEL6 {
PERFCOUNTER_STATE_SEL6_GLOBAL = 0x0,
PERFCOUNTER_STATE_SEL6_LOCAL = 0x1,
} PERFCOUNTER_STATE_SEL6;
typedef enum PERFCOUNTER_CNT7_STATE {
PERFCOUNTER_CNT7_STATE_RESET = 0x0,
PERFCOUNTER_CNT7_STATE_START = 0x1,
PERFCOUNTER_CNT7_STATE_FREEZE = 0x2,
PERFCOUNTER_CNT7_STATE_HW = 0x3,
} PERFCOUNTER_CNT7_STATE;
typedef enum PERFCOUNTER_STATE_SEL7 {
PERFCOUNTER_STATE_SEL7_GLOBAL = 0x0,
PERFCOUNTER_STATE_SEL7_LOCAL = 0x1,
} PERFCOUNTER_STATE_SEL7;
typedef enum PERFMON_STATE {
PERFMON_STATE_RESET = 0x0,
PERFMON_STATE_START = 0x1,
PERFMON_STATE_FREEZE = 0x2,
PERFMON_STATE_HW = 0x3,
} PERFMON_STATE;
typedef enum PERFMON_CNTOFF_AND_OR {
PERFMON_CNTOFF_OR = 0x0,
PERFMON_CNTOFF_AND = 0x1,
} PERFMON_CNTOFF_AND_OR;
typedef enum PERFMON_CNTOFF_INT_EN {
PERFMON_CNTOFF_INT_DISABLE = 0x0,
PERFMON_CNTOFF_INT_ENABLE = 0x1,
} PERFMON_CNTOFF_INT_EN;
typedef enum PERFMON_CNTOFF_INT_TYPE {
PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x0,
PERFMON_CNTOFF_INT_TYPE_PULSE = 0x1,
} PERFMON_CNTOFF_INT_TYPE;
typedef enum LptNumBanks {
LPT_NUM_BANKS_2BANK = 0x0,
LPT_NUM_BANKS_4BANK = 0x1,
LPT_NUM_BANKS_8BANK = 0x2,
LPT_NUM_BANKS_16BANK = 0x3,
LPT_NUM_BANKS_32BANK = 0x4,
} LptNumBanks;
typedef enum DCIO_DC_GENERICA_SEL {
DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x0,
DCIO_GENERICA_SEL_STEREOSYNC = 0x1,
DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2,
DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3,
DCIO_GENERICA_SEL_DVOA_CTL3 = 0x4,
DCIO_GENERICA_SEL_P1_PLLCLK = 0x5,
DCIO_GENERICA_SEL_P2_PLLCLK = 0x6,
DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x7,
DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x8,
DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x9,
DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa,
DCIO_GENERICA_SEL_SYNCEN = 0xb,
DCIO_GENERICA_SEL_GENERICA_SCG = 0xc,
DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0xd,
DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0xe,
DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0xf,
DCIO_GENERICA_SEL_GENERICA_DPRX = 0x10,
DCIO_GENERICA_SEL_GENERICB_DPRX = 0x11,
} DCIO_DC_GENERICA_SEL;
typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x0,
DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1,
DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2,
DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3,
DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x4,
DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x5,
DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x6,
DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 0x7,
DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 0x8,
} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
DCIO_UNIPHYA_FBDIV_CLK = 0x0,
DCIO_UNIPHYB_FBDIV_CLK = 0x1,
DCIO_UNIPHYC_FBDIV_CLK = 0x2,
DCIO_UNIPHYD_FBDIV_CLK = 0x3,
DCIO_UNIPHYE_FBDIV_CLK = 0x4,
DCIO_UNIPHYF_FBDIV_CLK = 0x5,
DCIO_UNIPHYG_FBDIV_CLK = 0x6,
DCIO_UNIPHYLPA_FBDIV_CLK = 0x7,
DCIO_UNIPHYLPB_FBDIV_CLK = 0x8,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x0,
DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1,
DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2,
DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3,
DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x4,
DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x5,
DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x6,
DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 0x7,
DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 0x8,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x0,
DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1,
DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2,
DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3,
DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x4,
DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x5,
DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x6,
DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 0x7,
DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 0x8,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
typedef enum DCIO_DC_GENERICB_SEL {
DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x0,
DCIO_GENERICB_SEL_STEREOSYNC = 0x1,
DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2,
DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3,
DCIO_GENERICB_SEL_DVOA_CTL3 = 0x4,
DCIO_GENERICB_SEL_P1_PLLCLK = 0x5,
DCIO_GENERICB_SEL_P2_PLLCLK = 0x6,
DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x7,
DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x8,
DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x9,
DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa,
DCIO_GENERICB_SEL_SYNCEN = 0xb,
DCIO_GENERICB_SEL_GENERICA_SCG = 0xc,
DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0xd,
DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0xe,
DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0xf,
} DCIO_DC_GENERICB_SEL;
typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x0,
DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1,
DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2,
DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3,
DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x4,
DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x5,
DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x6,
DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x7,
DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x8,
DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x9,
DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa,
DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0xb,
DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0xc,
DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0xd,
DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0xe,
DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0xf,
} DCIO_DC_PAD_EXTERN_SIG_SEL;
typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x0,
DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1,
DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2,
DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3,
} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x0,
DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1,
DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2,
DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3,
} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x0,
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1,
DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2,
DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3,
} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
typedef enum DCIO_DC_GPIO_VIP_DEBUG {
DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x0,
DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x1,
} DCIO_DC_GPIO_VIP_DEBUG;
typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x0,
DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x1,
DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2,
DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x3,
} DCIO_DC_GPIO_MACRO_DEBUG;
typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x0,
DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x1,
} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x0,
DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x1,
} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x0,
DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x1,
} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6,
DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7,
} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x0,
DCIO_UNIPHY_CHANNEL_INVERTED = 0x1,
} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x0,
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x1,
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3,
} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x0,
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x1,
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2,
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x3,
} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
DCIO_VIP_MUX_EN_DVO = 0x0,
DCIO_VIP_MUX_EN_VIP = 0x1,
} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x0,
DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x1,
} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x0,
DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x1,
} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0,
DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x0,
DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x0,
DCIO_LVTMA_SYNCEN_POL_INVERT = 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
DCIO_LVTMA_DIGON_OFF = 0x0,
DCIO_LVTMA_DIGON_ON = 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x0,
DCIO_LVTMA_DIGON_POL_INVERT = 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
DCIO_LVTMA_BLON_OFF = 0x0,
DCIO_LVTMA_BLON_ON = 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
DCIO_LVTMA_BLON_POL_NON_INVERT = 0x0,
DCIO_LVTMA_BLON_POL_INVERT = 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x0,
DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x1,
} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x0,
DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x1,
} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
DCIO_BL_PWM_DISABLE = 0x0,
DCIO_BL_PWM_ENABLE = 0x1,
} DCIO_BL_PWM_CNTL_BL_PWM_EN;
typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x0,
DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x1,
DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2,
DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x3,
} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x0,
DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x1,
} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x0,
DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x1,
} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x0,
DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x1,
} DCIO_BL_PWM_GRP1_REG_LOCK;
typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x0,
DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x1,
} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0,
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1,
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3,
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4,
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5,
} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0,
DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1,
} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x0,
DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x1,
} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
typedef enum DCIO_GSL_SEL {
DCIO_GSL_SEL_GROUP_0 = 0x0,
DCIO_GSL_SEL_GROUP_1 = 0x1,
DCIO_GSL_SEL_GROUP_2 = 0x2,
} DCIO_GSL_SEL;
typedef enum DCIO_GENLK_CLK_GSL_MASK {
DCIO_GENLK_CLK_GSL_MASK_NO = 0x0,
DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x1,
DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2,
} DCIO_GENLK_CLK_GSL_MASK;
typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x0,
DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1,
DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2,
} DCIO_GENLK_VSYNC_GSL_MASK;
typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x0,
DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x1,
DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2,
} DCIO_SWAPLOCK_A_GSL_MASK;
typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x0,
DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x1,
DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2,
} DCIO_SWAPLOCK_B_GSL_MASK;
typedef enum DCIO_GSL_VSYNC_SEL {
DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0,
DCIO_GSL_VSYNC_SEL_PIPE1 = 0x1,
DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2,
DCIO_GSL_VSYNC_SEL_PIPE3 = 0x3,
DCIO_GSL_VSYNC_SEL_PIPE4 = 0x4,
DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5,
} DCIO_GSL_VSYNC_SEL;
typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x0,
DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
} DCIO_GSL0_TIMING_SYNC_SEL;
typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x0,
DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
} DCIO_GSL1_TIMING_SYNC_SEL;
typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x0,
DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
} DCIO_GSL2_TIMING_SYNC_SEL;
typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
DCIO_GPU_TIMER_START_0_END_27 = 0x0,
DCIO_GPU_TIMER_START_1_END_28 = 0x1,
DCIO_GPU_TIMER_START_2_END_29 = 0x2,
DCIO_GPU_TIMER_START_3_END_30 = 0x3,
DCIO_GPU_TIMER_START_4_END_31 = 0x4,
DCIO_GPU_TIMER_START_6_END_33 = 0x5,
DCIO_GPU_TIMER_START_8_END_35 = 0x6,
DCIO_GPU_TIMER_START_10_END_37 = 0x7,
} DCIO_DC_GPU_TIMER_START_POSITION;
typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
DCIO_TEST_CLK_SEL_DISPCLK = 0x0,
DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x1,
DCIO_TEST_CLK_SEL_SCLK = 0x2,
} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x0,
DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x1,
} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x0,
DCIO_EXT_VSYNC_MUX_CRTC0 = 0x1,
DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2,
DCIO_EXT_VSYNC_MUX_CRTC2 = 0x3,
DCIO_EXT_VSYNC_MUX_CRTC3 = 0x4,
DCIO_EXT_VSYNC_MUX_CRTC4 = 0x5,
DCIO_EXT_VSYNC_MUX_CRTC5 = 0x6,
DCIO_EXT_VSYNC_MUX_GENERICB = 0x7,
} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
typedef enum DCIO_DCO_EXT_VSYNC_MASK {
DCIO_EXT_VSYNC_MASK_NONE = 0x0,
DCIO_EXT_VSYNC_MASK_PIPE0 = 0x1,
DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2,
DCIO_EXT_VSYNC_MASK_PIPE2 = 0x3,
DCIO_EXT_VSYNC_MASK_PIPE3 = 0x4,
DCIO_EXT_VSYNC_MASK_PIPE4 = 0x5,
DCIO_EXT_VSYNC_MASK_PIPE5 = 0x6,
DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x7,
} DCIO_DCO_EXT_VSYNC_MASK;
typedef enum DCIO_DBG_OUT_PIN_SEL {
DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x0,
DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x1,
} DCIO_DBG_OUT_PIN_SEL;
typedef enum DCIO_DBG_OUT_12BIT_SEL {
DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x0,
DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x1,
DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2,
DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x3,
} DCIO_DBG_OUT_12BIT_SEL;
typedef enum DCIO_DSYNC_SOFT_RESET {
DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x0,
DCIO_DSYNC_SOFT_RESET_ASSERT = 0x1,
} DCIO_DSYNC_SOFT_RESET;
typedef enum DCIO_DACA_SOFT_RESET {
DCIO_DACA_SOFT_RESET_DEASSERT = 0x0,
DCIO_DACA_SOFT_RESET_ASSERT = 0x1,
} DCIO_DACA_SOFT_RESET;
typedef enum DCIO_DCRXPHY_SOFT_RESET {
DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x0,
DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x1,
} DCIO_DCRXPHY_SOFT_RESET;
typedef enum DCIO_DPHY_LANE_SEL {
DCIO_DPHY_LANE_SEL_LANE0 = 0x0,
DCIO_DPHY_LANE_SEL_LANE1 = 0x1,
DCIO_DPHY_LANE_SEL_LANE2 = 0x2,
DCIO_DPHY_LANE_SEL_LANE3 = 0x3,
} DCIO_DPHY_LANE_SEL;
typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x0,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x1,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x3,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x5,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0xc,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0xd,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0xe,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0xf,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x10,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x11,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x18,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x19,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x1a,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x1b,
DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x1c,
DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d,
DCIO_GPU_TIMER_READ_SELECT_LOWER_DCFEV_P_FLIP = 0x24,
DCIO_GPU_TIMER_READ_SELECT_UPPER_DCFEV_P_FLIP = 0x25,
} DCIO_DC_GPU_TIMER_READ_SELECT;
typedef enum DCIO_IMPCAL_STEP_DELAY {
DCIO_IMPCAL_STEP_DELAY_1us = 0x0,
DCIO_IMPCAL_STEP_DELAY_2us = 0x1,
DCIO_IMPCAL_STEP_DELAY_3us = 0x2,
DCIO_IMPCAL_STEP_DELAY_4us = 0x3,
DCIO_IMPCAL_STEP_DELAY_5us = 0x4,
DCIO_IMPCAL_STEP_DELAY_6us = 0x5,
DCIO_IMPCAL_STEP_DELAY_7us = 0x6,
DCIO_IMPCAL_STEP_DELAY_8us = 0x7,
DCIO_IMPCAL_STEP_DELAY_9us = 0x8,
DCIO_IMPCAL_STEP_DELAY_10us = 0x9,
DCIO_IMPCAL_STEP_DELAY_11us = 0xa,
DCIO_IMPCAL_STEP_DELAY_12us = 0xb,
DCIO_IMPCAL_STEP_DELAY_13us = 0xc,
DCIO_IMPCAL_STEP_DELAY_14us = 0xd,
DCIO_IMPCAL_STEP_DELAY_15us = 0xe,
DCIO_IMPCAL_STEP_DELAY_16us = 0xf,
} DCIO_IMPCAL_STEP_DELAY;
typedef enum DCIO_UNIPHY_IMPCAL_SEL {
DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x0,
DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x1,
} DCIO_UNIPHY_IMPCAL_SEL;
typedef enum DCIOCHIP_HPD_SEL {
DCIOCHIP_HPD_SEL_ASYNC = 0x0,
DCIOCHIP_HPD_SEL_CLOCKED = 0x1,
} DCIOCHIP_HPD_SEL;
typedef enum DCIOCHIP_PAD_MODE {
DCIOCHIP_PAD_MODE_DDC = 0x0,
DCIOCHIP_PAD_MODE_DP = 0x1,
} DCIOCHIP_PAD_MODE;
typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x0,
DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x1,
} DCIOCHIP_AUXSLAVE_PAD_MODE;
typedef enum DCIOCHIP_INVERT {
DCIOCHIP_POL_NON_INVERT = 0x0,
DCIOCHIP_POL_INVERT = 0x1,
} DCIOCHIP_INVERT;
typedef enum DCIOCHIP_PD_EN {
DCIOCHIP_PD_EN_NOTALLOW = 0x0,
DCIOCHIP_PD_EN_ALLOW = 0x1,
} DCIOCHIP_PD_EN;
typedef enum DCIOCHIP_GPIO_MASK_EN {
DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x0,
DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x1,
} DCIOCHIP_GPIO_MASK_EN;
typedef enum DCIOCHIP_MASK {
DCIOCHIP_MASK_DISABLE = 0x0,
DCIOCHIP_MASK_ENABLE = 0x1,
} DCIOCHIP_MASK;
typedef enum DCIOCHIP_GPIO_I2C_MASK {
DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x0,
DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x1,
} DCIOCHIP_GPIO_I2C_MASK;
typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x0,
DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x1,
} DCIOCHIP_GPIO_I2C_DRIVE;
typedef enum DCIOCHIP_GPIO_I2C_EN {
DCIOCHIP_GPIO_I2C_DISABLE = 0x0,
DCIOCHIP_GPIO_I2C_ENABLE = 0x1,
} DCIOCHIP_GPIO_I2C_EN;
typedef enum DCIOCHIP_MASK_4BIT {
DCIOCHIP_MASK_4BIT_DISABLE = 0x0,
DCIOCHIP_MASK_4BIT_ENABLE = 0xf,
} DCIOCHIP_MASK_4BIT;
typedef enum DCIOCHIP_ENABLE_4BIT {
DCIOCHIP_4BIT_DISABLE = 0x0,
DCIOCHIP_4BIT_ENABLE = 0xf,
} DCIOCHIP_ENABLE_4BIT;
typedef enum DCIOCHIP_MASK_5BIT {
DCIOCHIP_MASIK_5BIT_DISABLE = 0x0,
DCIOCHIP_MASIK_5BIT_ENABLE = 0x1f,
} DCIOCHIP_MASK_5BIT;
typedef enum DCIOCHIP_ENABLE_5BIT {
DCIOCHIP_5BIT_DISABLE = 0x0,
DCIOCHIP_5BIT_ENABLE = 0x1f,
} DCIOCHIP_ENABLE_5BIT;
typedef enum DCIOCHIP_MASK_2BIT {
DCIOCHIP_MASK_2BIT_DISABLE = 0x0,
DCIOCHIP_MASK_2BIT_ENABLE = 0x3,
} DCIOCHIP_MASK_2BIT;
typedef enum DCIOCHIP_ENABLE_2BIT {
DCIOCHIP_2BIT_DISABLE = 0x0,
DCIOCHIP_2BIT_ENABLE = 0x3,
} DCIOCHIP_ENABLE_2BIT;
typedef enum DCIOCHIP_REF_27_SRC_SEL {
DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x0,
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x1,
DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2,
DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x3,
} DCIOCHIP_REF_27_SRC_SEL;
typedef enum DCIOCHIP_DVO_VREFPON {
DCIOCHIP_DVO_VREFPON_DISABLE = 0x0,
DCIOCHIP_DVO_VREFPON_ENABLE = 0x1,
} DCIOCHIP_DVO_VREFPON;
typedef enum DCIOCHIP_DVO_VREFSEL {
DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x0,
DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x1,
} DCIOCHIP_DVO_VREFSEL;
typedef enum DCP_GRPH_ENABLE {
DCP_GRPH_ENABLE_FALSE = 0x0,
DCP_GRPH_ENABLE_TRUE = 0x1,
} DCP_GRPH_ENABLE;
typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x0,
DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x1,
} DCP_GRPH_KEYER_ALPHA_SEL;
typedef enum DCP_GRPH_DEPTH {
DCP_GRPH_DEPTH_8BPP = 0x0,
DCP_GRPH_DEPTH_16BPP = 0x1,
DCP_GRPH_DEPTH_32BPP = 0x2,
DCP_GRPH_DEPTH_64BPP = 0x3,
} DCP_GRPH_DEPTH;
typedef enum DCP_GRPH_NUM_BANKS {
DCP_GRPH_NUM_BANKS_2BANK = 0x0,
DCP_GRPH_NUM_BANKS_4BANK = 0x1,
DCP_GRPH_NUM_BANKS_8BANK = 0x2,
DCP_GRPH_NUM_BANKS_16BANK = 0x3,
} DCP_GRPH_NUM_BANKS;
typedef enum DCP_GRPH_BANK_WIDTH {
DCP_GRPH_BANK_WIDTH_1 = 0x0,
DCP_GRPH_BANK_WIDTH_2 = 0x1,
DCP_GRPH_BANK_WIDTH_4 = 0x2,
DCP_GRPH_BANK_WIDTH_8 = 0x3,
} DCP_GRPH_BANK_WIDTH;
typedef enum DCP_GRPH_FORMAT {
DCP_GRPH_FORMAT_8BPP = 0x0,
DCP_GRPH_FORMAT_16BPP = 0x1,
DCP_GRPH_FORMAT_32BPP = 0x2,
DCP_GRPH_FORMAT_64BPP = 0x3,
} DCP_GRPH_FORMAT;
typedef enum DCP_GRPH_BANK_HEIGHT {
DCP_GRPH_BANK_HEIGHT_1 = 0x0,
DCP_GRPH_BANK_HEIGHT_2 = 0x1,
DCP_GRPH_BANK_HEIGHT_4 = 0x2,
DCP_GRPH_BANK_HEIGHT_8 = 0x3,
} DCP_GRPH_BANK_HEIGHT;
typedef enum DCP_GRPH_TILE_SPLIT {
DCP_GRPH_TILE_SPLIT_64B = 0x0,
DCP_GRPH_TILE_SPLIT_128B = 0x1,
DCP_GRPH_TILE_SPLIT_256B = 0x2,
DCP_GRPH_TILE_SPLIT_512B = 0x3,
DCP_GRPH_TILE_SPLIT_1B = 0x4,
DCP_GRPH_TILE_SPLIT_2B = 0x5,
DCP_GRPH_TILE_SPLIT_4B = 0x6,
} DCP_GRPH_TILE_SPLIT;
typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x0,
DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x1,
} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
typedef enum DCP_GRPH_PRIVILEGED_ACCESS_ENABLE {
DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE = 0x0,
DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE = 0x1,
} DCP_GRPH_PRIVILEGED_ACCESS_ENABLE;
typedef enum DCP_GRPH_MACRO_TILE_ASPECT {
DCP_GRPH_MACRO_TILE_ASPECT_1 = 0x0,
DCP_GRPH_MACRO_TILE_ASPECT_2 = 0x1,
DCP_GRPH_MACRO_TILE_ASPECT_4 = 0x2,
DCP_GRPH_MACRO_TILE_ASPECT_8 = 0x3,
} DCP_GRPH_MACRO_TILE_ASPECT;
typedef enum DCP_GRPH_ARRAY_MODE {
DCP_GRPH_ARRAY_MODE_0 = 0x0,
DCP_GRPH_ARRAY_MODE_1 = 0x1,
DCP_GRPH_ARRAY_MODE_2 = 0x2,
DCP_GRPH_ARRAY_MODE_3 = 0x3,
DCP_GRPH_ARRAY_MODE_4 = 0x4,
DCP_GRPH_ARRAY_MODE_7 = 0x7,
DCP_GRPH_ARRAY_MODE_12 = 0xc,
DCP_GRPH_ARRAY_MODE_13 = 0xd,
} DCP_GRPH_ARRAY_MODE;
typedef enum DCP_GRPH_MICRO_TILE_MODE {
DCP_GRPH_MICRO_TILE_MODE_0 = 0x0,
DCP_GRPH_MICRO_TILE_MODE_1 = 0x1,
DCP_GRPH_MICRO_TILE_MODE_2 = 0x2,
DCP_GRPH_MICRO_TILE_MODE_3 = 0x3,
} DCP_GRPH_MICRO_TILE_MODE;
typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x0,
DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x1,
} DCP_GRPH_COLOR_EXPANSION_MODE;
typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x0,
DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x1,
} DCP_GRPH_LUT_10BIT_BYPASS_EN;
typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x0,
DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x1,
} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
typedef enum DCP_GRPH_ENDIAN_SWAP {
DCP_GRPH_ENDIAN_SWAP_NONE = 0x0,
DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x1,
DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x2,
DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x3,
} DCP_GRPH_ENDIAN_SWAP;
typedef enum DCP_GRPH_RED_CROSSBAR {
DCP_GRPH_RED_CROSSBAR_FROM_R = 0x0,
DCP_GRPH_RED_CROSSBAR_FROM_G = 0x1,
DCP_GRPH_RED_CROSSBAR_FROM_B = 0x2,
DCP_GRPH_RED_CROSSBAR_FROM_A = 0x3,
} DCP_GRPH_RED_CROSSBAR;
typedef enum DCP_GRPH_GREEN_CROSSBAR {
DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x0,
DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x1,
DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x2,
DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x3,
} DCP_GRPH_GREEN_CROSSBAR;
typedef enum DCP_GRPH_BLUE_CROSSBAR {
DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x0,
DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x1,
DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x2,
DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x3,
} DCP_GRPH_BLUE_CROSSBAR;
typedef enum DCP_GRPH_ALPHA_CROSSBAR {
DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x0,
DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x1,
DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x2,
DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x3,
} DCP_GRPH_ALPHA_CROSSBAR;
typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x0,
DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x1,
} DCP_GRPH_PRIMARY_DFQ_ENABLE;
typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x0,
DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x1,
} DCP_GRPH_SECONDARY_DFQ_ENABLE;
typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x0,
DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x1,
} DCP_GRPH_INPUT_GAMMA_MODE;
typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x0,
DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x1,
} DCP_GRPH_MODE_UPDATE_PENDING;
typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x0,
DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x1,
} DCP_GRPH_MODE_UPDATE_TAKEN;
typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x0,
DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x1,
} DCP_GRPH_SURFACE_UPDATE_PENDING;
typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x0,
DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x1,
} DCP_GRPH_SURFACE_UPDATE_TAKEN;
typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x0,
DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x1,
} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
typedef enum DCP_GRPH_UPDATE_LOCK {
DCP_GRPH_UPDATE_LOCK_FALSE = 0x0,
DCP_GRPH_UPDATE_LOCK_TRUE = 0x1,
} DCP_GRPH_UPDATE_LOCK;
typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x0,
DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x1,
} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x0,
DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x1,
} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x0,
DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x1,
} DCP_GRPH_XDMA_SUPER_AA_EN;
typedef enum DCP_GRPH_DFQ_RESET {
DCP_GRPH_DFQ_RESET_FALSE = 0x0,
DCP_GRPH_DFQ_RESET_TRUE = 0x1,
} DCP_GRPH_DFQ_RESET;
typedef enum DCP_GRPH_DFQ_SIZE {
DCP_GRPH_DFQ_SIZE_DEEP1 = 0x0,
DCP_GRPH_DFQ_SIZE_DEEP2 = 0x1,
DCP_GRPH_DFQ_SIZE_DEEP3 = 0x2,
DCP_GRPH_DFQ_SIZE_DEEP4 = 0x3,
DCP_GRPH_DFQ_SIZE_DEEP5 = 0x4,
DCP_GRPH_DFQ_SIZE_DEEP6 = 0x5,
DCP_GRPH_DFQ_SIZE_DEEP7 = 0x6,
DCP_GRPH_DFQ_SIZE_DEEP8 = 0x7,
} DCP_GRPH_DFQ_SIZE;
typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x0,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x1,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x2,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x3,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x4,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x5,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x6,
DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x7,
} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
typedef enum DCP_GRPH_DFQ_RESET_ACK {
DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x0,
DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x1,
} DCP_GRPH_DFQ_RESET_ACK;
typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x0,
DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x1,
} DCP_GRPH_PFLIP_INT_CLEAR;
typedef enum DCP_GRPH_PFLIP_INT_MASK {
DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x0,
DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x1,
} DCP_GRPH_PFLIP_INT_MASK;
typedef enum DCP_GRPH_PFLIP_INT_TYPE {
DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x0,
DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x1,
} DCP_GRPH_PFLIP_INT_TYPE;
typedef enum DCP_GRPH_PRESCALE_SELECT {
DCP_GRPH_PRESCALE_SELECT_FIXED = 0x0,
DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x1,
} DCP_GRPH_PRESCALE_SELECT;
typedef enum DCP_GRPH_PRESCALE_R_SIGN {
DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x0,
DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x1,
} DCP_GRPH_PRESCALE_R_SIGN;
typedef enum DCP_GRPH_PRESCALE_G_SIGN {
DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x0,
DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x1,
} DCP_GRPH_PRESCALE_G_SIGN;
typedef enum DCP_GRPH_PRESCALE_B_SIGN {
DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x0,
DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x1,
} DCP_GRPH_PRESCALE_B_SIGN;
typedef enum DCP_GRPH_PRESCALE_BYPASS {
DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x0,
DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x1,
} DCP_GRPH_PRESCALE_BYPASS;
typedef enum DCP_INPUT_CSC_GRPH_MODE {
DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x0,
DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x1,
DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x2,
DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x3,
} DCP_INPUT_CSC_GRPH_MODE;
typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x0,
DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x1,
DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x2,
DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x3,
DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x4,
DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x5,
DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x6,
DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x7,
} DCP_OUTPUT_CSC_GRPH_MODE;
typedef enum DCP_DENORM_MODE {
DCP_DENORM_MODE_UNITY = 0x0,
DCP_DENORM_MODE_6BIT = 0x1,
DCP_DENORM_MODE_8BIT = 0x2,
DCP_DENORM_MODE_10BIT = 0x3,
DCP_DENORM_MODE_11BIT = 0x4,
DCP_DENORM_MODE_12BIT = 0x5,
DCP_DENORM_MODE_RESERVED0 = 0x6,
DCP_DENORM_MODE_RESERVED1 = 0x7,
} DCP_DENORM_MODE;
typedef enum DCP_DENORM_14BIT_OUT {
DCP_DENORM_14BIT_OUT_FALSE = 0x0,
DCP_DENORM_14BIT_OUT_TRUE = 0x1,
} DCP_DENORM_14BIT_OUT;
typedef enum DCP_OUT_ROUND_TRUNC_MODE {
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x0,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x1,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x2,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x3,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x4,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x5,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x6,
DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x7,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x8,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x9,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0xa,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0xb,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0xc,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0xd,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0xe,
DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0xf,
} DCP_OUT_ROUND_TRUNC_MODE;
typedef enum DCP_KEY_MODE {
DCP_KEY_MODE_ALPHA0 = 0x0,
DCP_KEY_MODE_ALPHA1 = 0x1,
DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x2,
DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x3,
} DCP_KEY_MODE;
typedef enum DCP_GRPH_DEGAMMA_MODE {
DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x0,
DCP_GRPH_DEGAMMA_MODE_ROMA = 0x1,
DCP_GRPH_DEGAMMA_MODE_ROMB = 0x2,
DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x3,
} DCP_GRPH_DEGAMMA_MODE;
typedef enum DCP_CURSOR2_DEGAMMA_MODE {
DCP_CURSOR2_DEGAMMA_MODE_BYPASS = 0x0,
DCP_CURSOR2_DEGAMMA_MODE_ROMA = 0x1,
DCP_CURSOR2_DEGAMMA_MODE_ROMB = 0x2,
DCP_CURSOR2_DEGAMMA_MODE_RESERVED = 0x3,
} DCP_CURSOR2_DEGAMMA_MODE;
typedef enum DCP_CURSOR_DEGAMMA_MODE {
DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x0,
DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x1,
DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x2,
DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x3,
} DCP_CURSOR_DEGAMMA_MODE;
typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x0,
DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x1,
DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x2,
DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x3,
} DCP_GRPH_GAMUT_REMAP_MODE;
typedef enum DCP_SPATIAL_DITHER_EN {
DCP_SPATIAL_DITHER_EN_FALSE = 0x0,
DCP_SPATIAL_DITHER_EN_TRUE = 0x1,
} DCP_SPATIAL_DITHER_EN;
typedef enum DCP_SPATIAL_DITHER_MODE {
DCP_SPATIAL_DITHER_MODE_BYPASS = 0x0,
DCP_SPATIAL_DITHER_MODE_ROMA = 0x1,
DCP_SPATIAL_DITHER_MODE_ROMB = 0x2,
DCP_SPATIAL_DITHER_MODE_RESERVED = 0x3,
} DCP_SPATIAL_DITHER_MODE;
typedef enum DCP_SPATIAL_DITHER_DEPTH {
DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x0,
DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x1,
DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x2,
DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x3,
} DCP_SPATIAL_DITHER_DEPTH;
typedef enum DCP_FRAME_RANDOM_ENABLE {
DCP_FRAME_RANDOM_ENABLE_FALSE = 0x0,
DCP_FRAME_RANDOM_ENABLE_TRUE = 0x1,
} DCP_FRAME_RANDOM_ENABLE;
typedef enum DCP_RGB_RANDOM_ENABLE {
DCP_RGB_RANDOM_ENABLE_FALSE = 0x0,
DCP_RGB_RANDOM_ENABLE_TRUE = 0x1,
} DCP_RGB_RANDOM_ENABLE;
typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x0,
DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x1,
} DCP_HIGHPASS_RANDOM_ENABLE;
typedef enum DCP_CURSOR_EN {
DCP_CURSOR_EN_FALSE = 0x0,
DCP_CURSOR_EN_TRUE = 0x1,
} DCP_CURSOR_EN;
typedef enum DCP_CUR_INV_TRANS_CLAMP {
DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x0,
DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x1,
} DCP_CUR_INV_TRANS_CLAMP;
typedef enum DCP_CURSOR_MODE {
DCP_CURSOR_MODE_MONO_2BPP = 0x0,
DCP_CURSOR_MODE_24BPP_1BIT = 0x1,
DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x2,
DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x3,
} DCP_CURSOR_MODE;
typedef enum DCP_CURSOR_2X_MAGNIFY {
DCP_CURSOR_2X_MAGNIFY_FALSE = 0x0,
DCP_CURSOR_2X_MAGNIFY_TRUE = 0x1,
} DCP_CURSOR_2X_MAGNIFY;
typedef enum DCP_CURSOR_FORCE_MC_ON {
DCP_CURSOR_FORCE_MC_ON_FALSE = 0x0,
DCP_CURSOR_FORCE_MC_ON_TRUE = 0x1,
} DCP_CURSOR_FORCE_MC_ON;
typedef enum DCP_CURSOR_URGENT_CONTROL {
DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x0,
DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x1,
DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x2,
DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x3,
DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x4,
} DCP_CURSOR_URGENT_CONTROL;
typedef enum DCP_CURSOR_UPDATE_PENDING {
DCP_CURSOR_UPDATE_PENDING_FALSE = 0x0,
DCP_CURSOR_UPDATE_PENDING_TRUE = 0x1,
} DCP_CURSOR_UPDATE_PENDING;
typedef enum DCP_CURSOR_UPDATE_TAKEN {
DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x0,
DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x1,
} DCP_CURSOR_UPDATE_TAKEN;
typedef enum DCP_CURSOR_UPDATE_LOCK {
DCP_CURSOR_UPDATE_LOCK_FALSE = 0x0,
DCP_CURSOR_UPDATE_LOCK_TRUE = 0x1,
} DCP_CURSOR_UPDATE_LOCK;
typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x0,
DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1,
DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x2,
DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3,
} DCP_CURSOR_UPDATE_STEREO_MODE;
typedef enum DCP_CURSOR2_EN {
DCP_CURSOR2_EN_FALSE = 0x0,
DCP_CURSOR2_EN_TRUE = 0x1,
} DCP_CURSOR2_EN;
typedef enum DCP_CUR2_INV_TRANS_CLAMP {
DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x0,
DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x1,
} DCP_CUR2_INV_TRANS_CLAMP;
typedef enum DCP_CURSOR2_MODE {
DCP_CURSOR2_MODE_MONO_2BPP = 0x0,
DCP_CURSOR2_MODE_24BPP_1BIT = 0x1,
DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI = 0x2,
DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI = 0x3,
} DCP_CURSOR2_MODE;
typedef enum DCP_CURSOR2_2X_MAGNIFY {
DCP_CURSOR2_2X_MAGNIFY_FALSE = 0x0,
DCP_CURSOR2_2X_MAGNIFY_TRUE = 0x1,
} DCP_CURSOR2_2X_MAGNIFY;
typedef enum DCP_CURSOR2_FORCE_MC_ON {
DCP_CURSOR2_FORCE_MC_ON_FALSE = 0x0,
DCP_CURSOR2_FORCE_MC_ON_TRUE = 0x1,
} DCP_CURSOR2_FORCE_MC_ON;
typedef enum DCP_CURSOR2_URGENT_CONTROL {
DCP_CURSOR2_URGENT_CONTROL_MODE_0 = 0x0,
DCP_CURSOR2_URGENT_CONTROL_MODE_1 = 0x1,
DCP_CURSOR2_URGENT_CONTROL_MODE_2 = 0x2,
DCP_CURSOR2_URGENT_CONTROL_MODE_3 = 0x3,
DCP_CURSOR2_URGENT_CONTROL_MODE_4 = 0x4,
} DCP_CURSOR2_URGENT_CONTROL;
typedef enum DCP_CURSOR2_UPDATE_PENDING {
DCP_CURSOR2_UPDATE_PENDING_FALSE = 0x0,
DCP_CURSOR2_UPDATE_PENDING_TRUE = 0x1,
} DCP_CURSOR2_UPDATE_PENDING;
typedef enum DCP_CURSOR2_UPDATE_TAKEN {
DCP_CURSOR2_UPDATE_TAKEN_FALSE = 0x0,
DCP_CURSOR2_UPDATE_TAKEN_TRUE = 0x1,
} DCP_CURSOR2_UPDATE_TAKEN;
typedef enum DCP_CURSOR2_UPDATE_LOCK {
DCP_CURSOR2_UPDATE_LOCK_FALSE = 0x0,
DCP_CURSOR2_UPDATE_LOCK_TRUE = 0x1,
} DCP_CURSOR2_UPDATE_LOCK;
typedef enum DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE {
DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
} DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE;
typedef enum DCP_CURSOR2_UPDATE_STEREO_MODE {
DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH = 0x0,
DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1,
DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED = 0x2,
DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3,
} DCP_CURSOR2_UPDATE_STEREO_MODE;
typedef enum DCP_CUR_REQUEST_FILTER_DIS {
DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x0,
DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x1,
} DCP_CUR_REQUEST_FILTER_DIS;
typedef enum DCP_CURSOR_STEREO_EN {
DCP_CURSOR_STEREO_EN_FALSE = 0x0,
DCP_CURSOR_STEREO_EN_TRUE = 0x1,
} DCP_CURSOR_STEREO_EN;
typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x0,
DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x1,
} DCP_CURSOR_STEREO_OFFSET_YNX;
typedef enum DCP_CURSOR2_STEREO_EN {
DCP_CURSOR2_STEREO_EN_FALSE = 0x0,
DCP_CURSOR2_STEREO_EN_TRUE = 0x1,
} DCP_CURSOR2_STEREO_EN;
typedef enum DCP_CURSOR2_STEREO_OFFSET_YNX {
DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION = 0x0,
DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION = 0x1,
} DCP_CURSOR2_STEREO_OFFSET_YNX;
typedef enum DCP_DC_LUT_RW_MODE {
DCP_DC_LUT_RW_MODE_256_ENTRY = 0x0,
DCP_DC_LUT_RW_MODE_PWL = 0x1,
} DCP_DC_LUT_RW_MODE;
typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x0,
DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x1,
} DCP_DC_LUT_VGA_ACCESS_ENABLE;
typedef enum DCP_DC_LUT_AUTOFILL {
DCP_DC_LUT_AUTOFILL_FALSE = 0x0,
DCP_DC_LUT_AUTOFILL_TRUE = 0x1,
} DCP_DC_LUT_AUTOFILL;
typedef enum DCP_DC_LUT_AUTOFILL_DONE {
DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x0,
DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x1,
} DCP_DC_LUT_AUTOFILL_DONE;
typedef enum DCP_DC_LUT_INC_B {
DCP_DC_LUT_INC_B_NA = 0x0,
DCP_DC_LUT_INC_B_2 = 0x1,
DCP_DC_LUT_INC_B_4 = 0x2,
DCP_DC_LUT_INC_B_8 = 0x3,
DCP_DC_LUT_INC_B_16 = 0x4,
DCP_DC_LUT_INC_B_32 = 0x5,
DCP_DC_LUT_INC_B_64 = 0x6,
DCP_DC_LUT_INC_B_128 = 0x7,
DCP_DC_LUT_INC_B_256 = 0x8,
DCP_DC_LUT_INC_B_512 = 0x9,
} DCP_DC_LUT_INC_B;
typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x0,
DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x1,
} DCP_DC_LUT_DATA_B_SIGNED_EN;
typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x0,
DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x1,
} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
typedef enum DCP_DC_LUT_DATA_B_FORMAT {
DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x0,
DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x1,
DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x2,
DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x3,
} DCP_DC_LUT_DATA_B_FORMAT;
typedef enum DCP_DC_LUT_INC_G {
DCP_DC_LUT_INC_G_NA = 0x0,
DCP_DC_LUT_INC_G_2 = 0x1,
DCP_DC_LUT_INC_G_4 = 0x2,
DCP_DC_LUT_INC_G_8 = 0x3,
DCP_DC_LUT_INC_G_16 = 0x4,
DCP_DC_LUT_INC_G_32 = 0x5,
DCP_DC_LUT_INC_G_64 = 0x6,
DCP_DC_LUT_INC_G_128 = 0x7,
DCP_DC_LUT_INC_G_256 = 0x8,
DCP_DC_LUT_INC_G_512 = 0x9,
} DCP_DC_LUT_INC_G;
typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x0,
DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x1,
} DCP_DC_LUT_DATA_G_SIGNED_EN;
typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x0,
DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x1,
} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
typedef enum DCP_DC_LUT_DATA_G_FORMAT {
DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x0,
DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x1,
DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x2,
DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x3,
} DCP_DC_LUT_DATA_G_FORMAT;
typedef enum DCP_DC_LUT_INC_R {
DCP_DC_LUT_INC_R_NA = 0x0,
DCP_DC_LUT_INC_R_2 = 0x1,
DCP_DC_LUT_INC_R_4 = 0x2,
DCP_DC_LUT_INC_R_8 = 0x3,
DCP_DC_LUT_INC_R_16 = 0x4,
DCP_DC_LUT_INC_R_32 = 0x5,
DCP_DC_LUT_INC_R_64 = 0x6,
DCP_DC_LUT_INC_R_128 = 0x7,
DCP_DC_LUT_INC_R_256 = 0x8,
DCP_DC_LUT_INC_R_512 = 0x9,
} DCP_DC_LUT_INC_R;
typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x0,
DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x1,
} DCP_DC_LUT_DATA_R_SIGNED_EN;
typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x0,
DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x1,
} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
typedef enum DCP_DC_LUT_DATA_R_FORMAT {
DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x0,
DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x1,
DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x2,
DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x3,
} DCP_DC_LUT_DATA_R_FORMAT;
typedef enum DCP_CRC_ENABLE {
DCP_CRC_ENABLE_FALSE = 0x0,
DCP_CRC_ENABLE_TRUE = 0x1,
} DCP_CRC_ENABLE;
typedef enum DCP_CRC_SOURCE_SEL {
DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x0,
DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x1,
DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x2,
DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x4,
} DCP_CRC_SOURCE_SEL;
typedef enum DCP_CRC_LINE_SEL {
DCP_CRC_LINE_SEL_RESERVED = 0x0,
DCP_CRC_LINE_SEL_EVEN = 0x1,
DCP_CRC_LINE_SEL_ODD = 0x2,
DCP_CRC_LINE_SEL_BOTH = 0x3,
} DCP_CRC_LINE_SEL;
typedef enum DCP_GRPH_FLIP_RATE {
DCP_GRPH_FLIP_RATE_1FRAME = 0x0,
DCP_GRPH_FLIP_RATE_2FRAME = 0x1,
DCP_GRPH_FLIP_RATE_3FRAME = 0x2,
DCP_GRPH_FLIP_RATE_4FRAME = 0x3,
DCP_GRPH_FLIP_RATE_5FRAME = 0x4,
DCP_GRPH_FLIP_RATE_6FRAME = 0x5,
DCP_GRPH_FLIP_RATE_7FRAME = 0x6,
DCP_GRPH_FLIP_RATE_8FRAME = 0x7,
} DCP_GRPH_FLIP_RATE;
typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x0,
DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x1,
} DCP_GRPH_FLIP_RATE_ENABLE;
typedef enum DCP_GSL0_EN {
DCP_GSL0_EN_FALSE = 0x0,
DCP_GSL0_EN_TRUE = 0x1,
} DCP_GSL0_EN;
typedef enum DCP_GSL1_EN {
DCP_GSL1_EN_FALSE = 0x0,
DCP_GSL1_EN_TRUE = 0x1,
} DCP_GSL1_EN;
typedef enum DCP_GSL2_EN {
DCP_GSL2_EN_FALSE = 0x0,
DCP_GSL2_EN_TRUE = 0x1,
} DCP_GSL2_EN;
typedef enum DCP_GSL_MASTER_EN {
DCP_GSL_MASTER_EN_FALSE = 0x0,
DCP_GSL_MASTER_EN_TRUE = 0x1,
} DCP_GSL_MASTER_EN;
typedef enum DCP_GSL_XDMA_GROUP {
DCP_GSL_XDMA_GROUP_VSYNC = 0x0,
DCP_GSL_XDMA_GROUP_HSYNC0 = 0x1,
DCP_GSL_XDMA_GROUP_HSYNC1 = 0x2,
DCP_GSL_XDMA_GROUP_HSYNC2 = 0x3,
} DCP_GSL_XDMA_GROUP;
typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x0,
DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x1,
} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
typedef enum DCP_GSL_SYNC_SOURCE {
DCP_GSL_SYNC_SOURCE_FLIP = 0x0,
DCP_GSL_SYNC_SOURCE_PHASE0 = 0x1,
DCP_GSL_SYNC_SOURCE_RESET = 0x2,
DCP_GSL_SYNC_SOURCE_PHASE1 = 0x3,
} DCP_GSL_SYNC_SOURCE;
typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x0,
DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x1,
} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
typedef enum DCP_TEST_DEBUG_WRITE_EN {
DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x0,
DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x1,
} DCP_TEST_DEBUG_WRITE_EN;
typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x0,
DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x1,
} DCP_GRPH_STEREOSYNC_FLIP_EN;
typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x0,
DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x1,
DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x2,
DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x3,
} DCP_GRPH_STEREOSYNC_FLIP_MODE;
typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x0,
DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x1,
} DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
typedef enum DCP_GRPH_ROTATION_ANGLE {
DCP_GRPH_ROTATION_ANGLE_0 = 0x0,
DCP_GRPH_ROTATION_ANGLE_90 = 0x1,
DCP_GRPH_ROTATION_ANGLE_180 = 0x2,
DCP_GRPH_ROTATION_ANGLE_270 = 0x3,
} DCP_GRPH_ROTATION_ANGLE;
typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x0,
DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x1,
} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x0,
DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE= 0x1,
} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
typedef enum DCP_GRPH_REGAMMA_MODE {
DCP_GRPH_REGAMMA_MODE_BYPASS = 0x0,
DCP_GRPH_REGAMMA_MODE_SRGB = 0x1,
DCP_GRPH_REGAMMA_MODE_XVYCC = 0x2,
DCP_GRPH_REGAMMA_MODE_PROGA = 0x3,
DCP_GRPH_REGAMMA_MODE_PROGB = 0x4,
} DCP_GRPH_REGAMMA_MODE;
typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x0,
DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x1,
} DCP_ALPHA_ROUND_TRUNC_MODE;
typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x0,
DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x1,
} DCP_CURSOR_ALPHA_BLND_ENA;
typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x0,
DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x1,
} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x0,
DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x1,
} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x0,
DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x1,
} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x0,
DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x1,
} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x0,
DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x1,
} DCP_GRPH_SURFACE_COUNTER_EN;
typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x0,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x1,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x2,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x3,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x4,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x5,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x6,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x7,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x8,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x9,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0xa,
DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0xb,
} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x0,
DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x1,
} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
typedef enum HDMI_KEEPOUT_MODE {
HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x0,
HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x1,
} HDMI_KEEPOUT_MODE;
typedef enum HDMI_CLOCK_CHANNEL_RATE {
HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x0,
HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x1,
} HDMI_CLOCK_CHANNEL_RATE;
typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x0,
HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x1,
} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
typedef enum HDMI_PACKET_GEN_VERSION {
HDMI_PACKET_GEN_VERSION_OLD = 0x0,
HDMI_PACKET_GEN_VERSION_NEW = 0x1,
} HDMI_PACKET_GEN_VERSION;
typedef enum HDMI_ERROR_ACK {
HDMI_ERROR_ACK_INT = 0x0,
HDMI_ERROR_NOT_ACK = 0x1,
} HDMI_ERROR_ACK;
typedef enum HDMI_ERROR_MASK {
HDMI_ERROR_MASK_INT = 0x0,
HDMI_ERROR_NOT_MASK = 0x1,
} HDMI_ERROR_MASK;
typedef enum HDMI_DEEP_COLOR_DEPTH {
HDMI_DEEP_COLOR_DEPTH_24BPP = 0x0,
HDMI_DEEP_COLOR_DEPTH_30BPP = 0x1,
HDMI_DEEP_COLOR_DEPTH_36BPP = 0x2,
HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x3,
} HDMI_DEEP_COLOR_DEPTH;
typedef enum HDMI_AUDIO_DELAY_EN {
HDMI_AUDIO_DELAY_DISABLE = 0x0,
HDMI_AUDIO_DELAY_58CLK = 0x1,
HDMI_AUDIO_DELAY_56CLK = 0x2,
HDMI_AUDIO_DELAY_RESERVED = 0x3,
} HDMI_AUDIO_DELAY_EN;
typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x0,
HDMI_SEND_MAX_AUDIO_PACKETS = 0x1,
} HDMI_AUDIO_SEND_MAX_PACKETS;
typedef enum HDMI_ACR_SEND {
HDMI_ACR_NOT_SEND = 0x0,
HDMI_ACR_PKT_SEND = 0x1,
} HDMI_ACR_SEND;
typedef enum HDMI_ACR_CONT {
HDMI_ACR_CONT_DISABLE = 0x0,
HDMI_ACR_CONT_ENABLE = 0x1,
} HDMI_ACR_CONT;
typedef enum HDMI_ACR_SELECT {
HDMI_ACR_SELECT_HW = 0x0,
HDMI_ACR_SELECT_32K = 0x1,
HDMI_ACR_SELECT_44K = 0x2,
HDMI_ACR_SELECT_48K = 0x3,
} HDMI_ACR_SELECT;
typedef enum HDMI_ACR_SOURCE {
HDMI_ACR_SOURCE_HW = 0x0,
HDMI_ACR_SOURCE_SW = 0x1,
} HDMI_ACR_SOURCE;
typedef enum HDMI_ACR_N_MULTIPLE {
HDMI_ACR_0_MULTIPLE_RESERVED = 0x0,
HDMI_ACR_1_MULTIPLE = 0x1,
HDMI_ACR_2_MULTIPLE = 0x2,
HDMI_ACR_3_MULTIPLE_RESERVED = 0x3,
HDMI_ACR_4_MULTIPLE = 0x4,
HDMI_ACR_5_MULTIPLE_RESERVED = 0x5,
HDMI_ACR_6_MULTIPLE_RESERVED = 0x6,
HDMI_ACR_7_MULTIPLE_RESERVED = 0x7,
} HDMI_ACR_N_MULTIPLE;
typedef enum HDMI_ACR_AUDIO_PRIORITY {
HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x0,
HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x1,
} HDMI_ACR_AUDIO_PRIORITY;
typedef enum HDMI_NULL_SEND {
HDMI_NULL_NOT_SEND = 0x0,
HDMI_NULL_PKT_SEND = 0x1,
} HDMI_NULL_SEND;
typedef enum HDMI_GC_SEND {
HDMI_GC_NOT_SEND = 0x0,
HDMI_GC_PKT_SEND = 0x1,
} HDMI_GC_SEND;
typedef enum HDMI_GC_CONT {
HDMI_GC_CONT_DISABLE = 0x0,
HDMI_GC_CONT_ENABLE = 0x1,
} HDMI_GC_CONT;
typedef enum HDMI_ISRC_SEND {
HDMI_ISRC_NOT_SEND = 0x0,
HDMI_ISRC_PKT_SEND = 0x1,
} HDMI_ISRC_SEND;
typedef enum HDMI_ISRC_CONT {
HDMI_ISRC_CONT_DISABLE = 0x0,
HDMI_ISRC_CONT_ENABLE = 0x1,
} HDMI_ISRC_CONT;
typedef enum HDMI_AVI_INFO_SEND {
HDMI_AVI_INFO_NOT_SEND = 0x0,
HDMI_AVI_INFO_PKT_SEND = 0x1,
} HDMI_AVI_INFO_SEND;
typedef enum HDMI_AVI_INFO_CONT {
HDMI_AVI_INFO_CONT_DISABLE = 0x0,
HDMI_AVI_INFO_CONT_ENABLE = 0x1,
} HDMI_AVI_INFO_CONT;
typedef enum HDMI_AUDIO_INFO_SEND {
HDMI_AUDIO_INFO_NOT_SEND = 0x0,
HDMI_AUDIO_INFO_PKT_SEND = 0x1,
} HDMI_AUDIO_INFO_SEND;
typedef enum HDMI_AUDIO_INFO_CONT {
HDMI_AUDIO_INFO_CONT_DISABLE = 0x0,
HDMI_AUDIO_INFO_CONT_ENABLE = 0x1,
} HDMI_AUDIO_INFO_CONT;
typedef enum HDMI_MPEG_INFO_SEND {
HDMI_MPEG_INFO_NOT_SEND = 0x0,
HDMI_MPEG_INFO_PKT_SEND = 0x1,
} HDMI_MPEG_INFO_SEND;
typedef enum HDMI_MPEG_INFO_CONT {
HDMI_MPEG_INFO_CONT_DISABLE = 0x0,
HDMI_MPEG_INFO_CONT_ENABLE = 0x1,
} HDMI_MPEG_INFO_CONT;
typedef enum HDMI_GENERIC0_SEND {
HDMI_GENERIC0_NOT_SEND = 0x0,
HDMI_GENERIC0_PKT_SEND = 0x1,
} HDMI_GENERIC0_SEND;
typedef enum HDMI_GENERIC0_CONT {
HDMI_GENERIC0_CONT_DISABLE = 0x0,
HDMI_GENERIC0_CONT_ENABLE = 0x1,
} HDMI_GENERIC0_CONT;
typedef enum HDMI_GENERIC1_SEND {
HDMI_GENERIC1_NOT_SEND = 0x0,
HDMI_GENERIC1_PKT_SEND = 0x1,
} HDMI_GENERIC1_SEND;
typedef enum HDMI_GENERIC1_CONT {
HDMI_GENERIC1_CONT_DISABLE = 0x0,
HDMI_GENERIC1_CONT_ENABLE = 0x1,
} HDMI_GENERIC1_CONT;
typedef enum HDMI_GC_AVMUTE_CONT {
HDMI_GC_AVMUTE_CONT_DISABLE = 0x0,
HDMI_GC_AVMUTE_CONT_ENABLE = 0x1,
} HDMI_GC_AVMUTE_CONT;
typedef enum HDMI_PACKING_PHASE_OVERRIDE {
HDMI_PACKING_PHASE_SET_BY_HW = 0x0,
HDMI_PACKING_PHASE_SET_BY_SW = 0x1,
} HDMI_PACKING_PHASE_OVERRIDE;
typedef enum HDMI_GENERIC2_SEND {
HDMI_GENERIC2_NOT_SEND = 0x0,
HDMI_GENERIC2_PKT_SEND = 0x1,
} HDMI_GENERIC2_SEND;
typedef enum HDMI_GENERIC2_CONT {
HDMI_GENERIC2_CONT_DISABLE = 0x0,
HDMI_GENERIC2_CONT_ENABLE = 0x1,
} HDMI_GENERIC2_CONT;
typedef enum HDMI_GENERIC3_SEND {
HDMI_GENERIC3_NOT_SEND = 0x0,
HDMI_GENERIC3_PKT_SEND = 0x1,
} HDMI_GENERIC3_SEND;
typedef enum HDMI_GENERIC3_CONT {
HDMI_GENERIC3_CONT_DISABLE = 0x0,
HDMI_GENERIC3_CONT_ENABLE = 0x1,
} HDMI_GENERIC3_CONT;
typedef enum TMDS_PIXEL_ENCODING {
TMDS_PIXEL_ENCODING_444 = 0x0,
TMDS_PIXEL_ENCODING_422 = 0x1,
} TMDS_PIXEL_ENCODING;
typedef enum TMDS_COLOR_FORMAT {
TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP= 0x0,
TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x1,
TMDS_COLOR_FORMAT_DUAL30BPP = 0x2,
TMDS_COLOR_FORMAT_RESERVED = 0x3,
} TMDS_COLOR_FORMAT;
typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
TMDS_STEREOSYNC_CTL0 = 0x0,
TMDS_STEREOSYNC_CTL1 = 0x1,
TMDS_STEREOSYNC_CTL2 = 0x2,
TMDS_STEREOSYNC_CTL3 = 0x3,
} TMDS_STEREOSYNC_CTL_SEL_REG;
typedef enum TMDS_CTL0_DATA_SEL {
TMDS_CTL0_DATA_SEL0_RESERVED = 0x0,
TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x1,
TMDS_CTL0_DATA_SEL2_VSYNC = 0x2,
TMDS_CTL0_DATA_SEL3_RESERVED = 0x3,
TMDS_CTL0_DATA_SEL4_HSYNC = 0x4,
TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x5,
TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x6,
TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x7,
} TMDS_CTL0_DATA_SEL;
typedef enum TMDS_CTL0_DATA_DELAY {
TMDS_CTL0_DATA_DELAY_0PIX = 0x0,
TMDS_CTL0_DATA_DELAY_1PIX = 0x1,
TMDS_CTL0_DATA_DELAY_2PIX = 0x2,
TMDS_CTL0_DATA_DELAY_3PIX = 0x3,
TMDS_CTL0_DATA_DELAY_4PIX = 0x4,
TMDS_CTL0_DATA_DELAY_5PIX = 0x5,
TMDS_CTL0_DATA_DELAY_6PIX = 0x6,
TMDS_CTL0_DATA_DELAY_7PIX = 0x7,
} TMDS_CTL0_DATA_DELAY;
typedef enum TMDS_CTL0_DATA_INVERT {
TMDS_CTL0_DATA_NORMAL = 0x0,
TMDS_CTL0_DATA_INVERT_EN = 0x1,
} TMDS_CTL0_DATA_INVERT;
typedef enum TMDS_CTL0_DATA_MODULATION {
TMDS_CTL0_DATA_MODULATION_DISABLE = 0x0,
TMDS_CTL0_DATA_MODULATION_BIT0 = 0x1,
TMDS_CTL0_DATA_MODULATION_BIT1 = 0x2,
TMDS_CTL0_DATA_MODULATION_BIT2 = 0x3,
} TMDS_CTL0_DATA_MODULATION;
typedef enum TMDS_CTL0_PATTERN_OUT_EN {
TMDS_CTL0_PATTERN_OUT_DISABLE = 0x0,
TMDS_CTL0_PATTERN_OUT_ENABLE = 0x1,
} TMDS_CTL0_PATTERN_OUT_EN;
typedef enum TMDS_CTL1_DATA_SEL {
TMDS_CTL1_DATA_SEL0_RESERVED = 0x0,
TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x1,
TMDS_CTL1_DATA_SEL2_VSYNC = 0x2,
TMDS_CTL1_DATA_SEL3_RESERVED = 0x3,
TMDS_CTL1_DATA_SEL4_HSYNC = 0x4,
TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x5,
TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x6,
TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x7,
} TMDS_CTL1_DATA_SEL;
typedef enum TMDS_CTL1_DATA_DELAY {
TMDS_CTL1_DATA_DELAY_0PIX = 0x0,
TMDS_CTL1_DATA_DELAY_1PIX = 0x1,
TMDS_CTL1_DATA_DELAY_2PIX = 0x2,
TMDS_CTL1_DATA_DELAY_3PIX = 0x3,
TMDS_CTL1_DATA_DELAY_4PIX = 0x4,
TMDS_CTL1_DATA_DELAY_5PIX = 0x5,
TMDS_CTL1_DATA_DELAY_6PIX = 0x6,
TMDS_CTL1_DATA_DELAY_7PIX = 0x7,
} TMDS_CTL1_DATA_DELAY;
typedef enum TMDS_CTL1_DATA_INVERT {
TMDS_CTL1_DATA_NORMAL = 0x0,
TMDS_CTL1_DATA_INVERT_EN = 0x1,
} TMDS_CTL1_DATA_INVERT;
typedef enum TMDS_CTL1_DATA_MODULATION {
TMDS_CTL1_DATA_MODULATION_DISABLE = 0x0,
TMDS_CTL1_DATA_MODULATION_BIT0 = 0x1,
TMDS_CTL1_DATA_MODULATION_BIT1 = 0x2,
TMDS_CTL1_DATA_MODULATION_BIT2 = 0x3,
} TMDS_CTL1_DATA_MODULATION;
typedef enum TMDS_CTL1_PATTERN_OUT_EN {
TMDS_CTL1_PATTERN_OUT_DISABLE = 0x0,
TMDS_CTL1_PATTERN_OUT_ENABLE = 0x1,
} TMDS_CTL1_PATTERN_OUT_EN;
typedef enum TMDS_CTL2_DATA_SEL {
TMDS_CTL2_DATA_SEL0_RESERVED = 0x0,
TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x1,
TMDS_CTL2_DATA_SEL2_VSYNC = 0x2,
TMDS_CTL2_DATA_SEL3_RESERVED = 0x3,
TMDS_CTL2_DATA_SEL4_HSYNC = 0x4,
TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x5,
TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x6,
TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x7,
} TMDS_CTL2_DATA_SEL;
typedef enum TMDS_CTL2_DATA_DELAY {
TMDS_CTL2_DATA_DELAY_0PIX = 0x0,
TMDS_CTL2_DATA_DELAY_1PIX = 0x1,
TMDS_CTL2_DATA_DELAY_2PIX = 0x2,
TMDS_CTL2_DATA_DELAY_3PIX = 0x3,
TMDS_CTL2_DATA_DELAY_4PIX = 0x4,
TMDS_CTL2_DATA_DELAY_5PIX = 0x5,
TMDS_CTL2_DATA_DELAY_6PIX = 0x6,
TMDS_CTL2_DATA_DELAY_7PIX = 0x7,
} TMDS_CTL2_DATA_DELAY;
typedef enum TMDS_CTL2_DATA_INVERT {
TMDS_CTL2_DATA_NORMAL = 0x0,
TMDS_CTL2_DATA_INVERT_EN = 0x1,
} TMDS_CTL2_DATA_INVERT;
typedef enum TMDS_CTL2_DATA_MODULATION {
TMDS_CTL2_DATA_MODULATION_DISABLE = 0x0,
TMDS_CTL2_DATA_MODULATION_BIT0 = 0x1,
TMDS_CTL2_DATA_MODULATION_BIT1 = 0x2,
TMDS_CTL2_DATA_MODULATION_BIT2 = 0x3,
} TMDS_CTL2_DATA_MODULATION;
typedef enum TMDS_CTL2_PATTERN_OUT_EN {
TMDS_CTL2_PATTERN_OUT_DISABLE = 0x0,
TMDS_CTL2_PATTERN_OUT_ENABLE = 0x1,
} TMDS_CTL2_PATTERN_OUT_EN;
typedef enum TMDS_CTL3_DATA_DELAY {
TMDS_CTL3_DATA_DELAY_0PIX = 0x0,
TMDS_CTL3_DATA_DELAY_1PIX = 0x1,
TMDS_CTL3_DATA_DELAY_2PIX = 0x2,
TMDS_CTL3_DATA_DELAY_3PIX = 0x3,
TMDS_CTL3_DATA_DELAY_4PIX = 0x4,
TMDS_CTL3_DATA_DELAY_5PIX = 0x5,
TMDS_CTL3_DATA_DELAY_6PIX = 0x6,
TMDS_CTL3_DATA_DELAY_7PIX = 0x7,
} TMDS_CTL3_DATA_DELAY;
typedef enum TMDS_CTL3_DATA_INVERT {
TMDS_CTL3_DATA_NORMAL = 0x0,
TMDS_CTL3_DATA_INVERT_EN = 0x1,
} TMDS_CTL3_DATA_INVERT;
typedef enum TMDS_CTL3_DATA_MODULATION {
TMDS_CTL3_DATA_MODULATION_DISABLE = 0x0,
TMDS_CTL3_DATA_MODULATION_BIT0 = 0x1,
TMDS_CTL3_DATA_MODULATION_BIT1 = 0x2,
TMDS_CTL3_DATA_MODULATION_BIT2 = 0x3,
} TMDS_CTL3_DATA_MODULATION;
typedef enum TMDS_CTL3_PATTERN_OUT_EN {
TMDS_CTL3_PATTERN_OUT_DISABLE = 0x0,
TMDS_CTL3_PATTERN_OUT_ENABLE = 0x1,
} TMDS_CTL3_PATTERN_OUT_EN;
typedef enum TMDS_CTL3_DATA_SEL {
TMDS_CTL3_DATA_SEL0_RESERVED = 0x0,
TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x1,
TMDS_CTL3_DATA_SEL2_VSYNC = 0x2,
TMDS_CTL3_DATA_SEL3_RESERVED = 0x3,
TMDS_CTL3_DATA_SEL4_HSYNC = 0x4,
TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x5,
TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x6,
TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x7,
} TMDS_CTL3_DATA_SEL;
typedef enum DIG_FE_CNTL_SOURCE_SELECT {
DIG_FE_SOURCE_FROM_FMT0 = 0x0,
DIG_FE_SOURCE_FROM_FMT1 = 0x1,
DIG_FE_SOURCE_FROM_FMT2 = 0x2,
DIG_FE_SOURCE_FROM_FMT3 = 0x3,
} DIG_FE_CNTL_SOURCE_SELECT;
typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
DIG_FE_STEREOSYNC_FROM_FMT0 = 0x0,
DIG_FE_STEREOSYNC_FROM_FMT1 = 0x1,
DIG_FE_STEREOSYNC_FROM_FMT2 = 0x2,
DIG_FE_STEREOSYNC_FROM_FMT3 = 0x3,
} DIG_FE_CNTL_STEREOSYNC_SELECT;
typedef enum DIG_FIFO_READ_CLOCK_SRC {
DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x0,
DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x1,
} DIG_FIFO_READ_CLOCK_SRC;
typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
DIG_OUTPUT_CRC_ON_LINK0 = 0x0,
DIG_OUTPUT_CRC_ON_LINK1 = 0x1,
} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
typedef enum DIG_OUTPUT_CRC_DATA_SEL {
DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x0,
DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x1,
DIG_OUTPUT_CRC_FOR_VBI = 0x2,
DIG_OUTPUT_CRC_FOR_AUDIO = 0x3,
} DIG_OUTPUT_CRC_DATA_SEL;
typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
DIG_IN_NORMAL_OPERATION = 0x0,
DIG_IN_DEBUG_MODE = 0x1,
} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
DIG_10BIT_TEST_PATTERN = 0x0,
DIG_ALTERNATING_TEST_PATTERN = 0x1,
} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
DIG_TEST_PATTERN_NORMAL = 0x0,
DIG_TEST_PATTERN_RANDOM = 0x1,
} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
DIG_RANDOM_PATTERN_ENABLED = 0x0,
DIG_RANDOM_PATTERN_RESETED = 0x1,
} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x0,
DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x1,
} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x0,
DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x1,
} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
DIG_FIFO_USE_OVERWRITE_LEVEL = 0x0,
DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x1,
} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
typedef enum DIG_FIFO_ERROR_ACK {
DIG_FIFO_ERROR_ACK_INT = 0x0,
DIG_FIFO_ERROR_NOT_ACK = 0x1,
} DIG_FIFO_ERROR_ACK;
typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x0,
DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x1,
} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x0,
DIG_FIFO_FORCE_RECOMP_MINMAX = 0x1,
} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
typedef enum DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT {
DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK = 0x0,
DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC = 0x1,
} DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT;
typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK {
DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT = 0x0,
DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK = 0x1,
} DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK;
typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK {
DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT = 0x0,
DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK = 0x1,
} DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK;
typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
AFMT_INTERRUPT_DISABLE = 0x0,
AFMT_INTERRUPT_ENABLE = 0x1,
} AFMT_INTERRUPT_STATUS_CHG_MASK;
typedef enum HDMI_GC_AVMUTE {
HDMI_GC_AVMUTE_SET = 0x0,
HDMI_GC_AVMUTE_UNSET = 0x1,
} HDMI_GC_AVMUTE;
typedef enum HDMI_DEFAULT_PAHSE {
HDMI_DEFAULT_PHASE_IS_0 = 0x0,
HDMI_DEFAULT_PHASE_IS_1 = 0x1,
} HDMI_DEFAULT_PAHSE;
typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS= 0x0,
AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x1,
} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
typedef enum AUDIO_LAYOUT_SELECT {
AUDIO_LAYOUT_0 = 0x0,
AUDIO_LAYOUT_1 = 0x1,
} AUDIO_LAYOUT_SELECT;
typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
AFMT_AUDIO_CRC_ONESHOT = 0x0,
AFMT_AUDIO_CRC_AUTO_RESTART = 0x1,
} AFMT_AUDIO_CRC_CONTROL_CONT;
typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x0,
AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x1,
} AFMT_AUDIO_CRC_CONTROL_SOURCE;
typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
AFMT_AUDIO_CRC_CH0_SIG = 0x0,
AFMT_AUDIO_CRC_CH1_SIG = 0x1,
AFMT_AUDIO_CRC_CH2_SIG = 0x2,
AFMT_AUDIO_CRC_CH3_SIG = 0x3,
AFMT_AUDIO_CRC_CH4_SIG = 0x4,
AFMT_AUDIO_CRC_CH5_SIG = 0x5,
AFMT_AUDIO_CRC_CH6_SIG = 0x6,
AFMT_AUDIO_CRC_CH7_SIG = 0x7,
AFMT_AUDIO_CRC_RESERVED = 0x8,
AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x9,
} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
typedef enum AFMT_RAMP_CONTROL0_SIGN {
AFMT_RAMP_SIGNED = 0x0,
AFMT_RAMP_UNSIGNED = 0x1,
} AFMT_RAMP_CONTROL0_SIGN;
typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
AFMT_AUDIO_PACKET_SENT_DISABLED = 0x0,
AFMT_AUDIO_PACKET_SENT_ENABLED = 0x1,
} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED= 0x0,
AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x1,
} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x0,
AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x1,
} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x0,
AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x1,
AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x2,
AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x3,
AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x4,
AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x5,
AFMT_AUDIO_SRC_RESERVED = 0x6,
} AFMT_AUDIO_SRC_CONTROL_SELECT;
typedef enum DIG_BE_CNTL_MODE {
DIG_BE_DP_SST_MODE = 0x0,
DIG_BE_RESERVED1 = 0x1,
DIG_BE_TMDS_DVI_MODE = 0x2,
DIG_BE_TMDS_HDMI_MODE = 0x3,
DIG_BE_SDVO_RESERVED = 0x4,
DIG_BE_DP_MST_MODE = 0x5,
DIG_BE_RESERVED2 = 0x6,
DIG_BE_RESERVED3 = 0x7,
} DIG_BE_CNTL_MODE;
typedef enum DIG_BE_CNTL_HPD_SELECT {
DIG_BE_CNTL_HPD1 = 0x0,
DIG_BE_CNTL_HPD2 = 0x1,
DIG_BE_CNTL_HPD3 = 0x2,
DIG_BE_CNTL_HPD4 = 0x3,
DIG_BE_CNTL_HPD5 = 0x4,
DIG_BE_CNTL_HPD6 = 0x5,
} DIG_BE_CNTL_HPD_SELECT;
typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x0,
LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x1,
} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
typedef enum TMDS_SYNC_PHASE {
TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x0,
TMDS_SYNC_PHASE_ON_FRAME_START = 0x1,
} TMDS_SYNC_PHASE;
typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x0,
TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x1,
} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x0,
TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x1,
} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x0,
TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x1,
} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x0,
TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x1,
} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x0,
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON= 0x1,
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x2,
TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x3,
} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x0,
TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x1,
} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x0,
TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x1,
} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x0,
TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x1,
} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x0,
TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x1,
} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x0,
TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x1,
} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x0,
TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x1,
} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x0,
TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x1,
} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x0,
TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x1,
} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x0,
TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x1,
} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x0,
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x1,
TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x2,
TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x3,
} TMDS_REG_TEST_OUTPUTA_CNTLA;
typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x0,
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x1,
TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x2,
TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x3,
} TMDS_REG_TEST_OUTPUTB_CNTLB;
typedef enum DP_LINK_TRAINING_COMPLETE {
DP_LINK_TRAINING_NOT_COMPLETE = 0x0,
DP_LINK_TRAINING_ALREADY_COMPLETE = 0x1,
} DP_LINK_TRAINING_COMPLETE;
typedef enum DP_EMBEDDED_PANEL_MODE {
DP_EXTERNAL_PANEL = 0x0,
DP_EMBEDDED_PANEL = 0x1,
} DP_EMBEDDED_PANEL_MODE;
typedef enum DP_PIXEL_ENCODING {
DP_PIXEL_ENCODING_RGB444 = 0x0,
DP_PIXEL_ENCODING_YCBCR422 = 0x1,
DP_PIXEL_ENCODING_YCBCR444 = 0x2,
DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x3,
DP_PIXEL_ENCODING_Y_ONLY = 0x4,
DP_PIXEL_ENCODING_RESERVED = 0x5,
} DP_PIXEL_ENCODING;
typedef enum DP_DYN_RANGE {
DP_DYN_VESA_RANGE = 0x0,
DP_DYN_CEA_RANGE = 0x1,
} DP_DYN_RANGE;
typedef enum DP_YCBCR_RANGE {
DP_YCBCR_RANGE_BT601_5 = 0x0,
DP_YCBCR_RANGE_BT709_5 = 0x1,
} DP_YCBCR_RANGE;
typedef enum DP_COMPONENT_DEPTH {
DP_COMPONENT_DEPTH_6BPC = 0x0,
DP_COMPONENT_DEPTH_8BPC = 0x1,
DP_COMPONENT_DEPTH_10BPC = 0x2,
DP_COMPONENT_DEPTH_12BPC = 0x3,
DP_COMPONENT_DEPTH_16BPC = 0x4,
DP_COMPONENT_DEPTH_RESERVED = 0x5,
} DP_COMPONENT_DEPTH;
typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
MSA_MISC0_OVERRIDE_DISABLE = 0x0,
MSA_MISC0_OVERRIDE_ENABLE = 0x1,
} DP_MSA_MISC0_OVERRIDE_ENABLE;
typedef enum DP_UDI_LANES {
DP_UDI_1_LANE = 0x0,
DP_UDI_2_LANES = 0x1,
DP_UDI_LANES_RESERVED = 0x2,
DP_UDI_4_LANES = 0x3,
} DP_UDI_LANES;
typedef enum DP_VID_STREAM_DIS_DEFER {
DP_VID_STREAM_DIS_NO_DEFER = 0x0,
DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x1,
DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x2,
} DP_VID_STREAM_DIS_DEFER;
typedef enum DP_STEER_OVERFLOW_ACK {
DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x0,
DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x1,
} DP_STEER_OVERFLOW_ACK;
typedef enum DP_STEER_OVERFLOW_MASK {
DP_STEER_OVERFLOW_MASKED = 0x0,
DP_STEER_OVERFLOW_UNMASK = 0x1,
} DP_STEER_OVERFLOW_MASK;
typedef enum DP_TU_OVERFLOW_ACK {
DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x0,
DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x1,
} DP_TU_OVERFLOW_ACK;
typedef enum DP_VID_TIMING_MODE {
DP_VID_TIMING_MODE_ASYNC = 0x0,
DP_VID_TIMING_MODE_SYNC = 0x1,
} DP_VID_TIMING_MODE;
typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x0,
DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x1,
} DP_VID_M_N_DOUBLE_BUFFER_MODE;
typedef enum DP_VID_M_N_GEN_EN {
DP_VID_M_N_PROGRAMMED_VIA_REG = 0x0,
DP_VID_M_N_CALC_AUTO = 0x1,
} DP_VID_M_N_GEN_EN;
typedef enum DP_VID_ENHANCED_FRAME_MODE {
VID_NORMAL_FRAME_MODE = 0x0,
VID_ENHANCED_MODE = 0x1,
} DP_VID_ENHANCED_FRAME_MODE;
typedef enum DP_VID_MSA_TOP_FIELD_MODE {
DP_TOP_FIELD_ONLY = 0x0,
DP_TOP_PLUS_BOTTOM_FIELD = 0x1,
} DP_VID_MSA_TOP_FIELD_MODE;
typedef enum DP_VID_VBID_FIELD_POL {
DP_VID_VBID_FIELD_POL_NORMAL = 0x0,
DP_VID_VBID_FIELD_POL_INV = 0x1,
} DP_VID_VBID_FIELD_POL;
typedef enum DP_VID_STREAM_DISABLE_ACK {
ID_STREAM_DISABLE_NO_ACK = 0x0,
ID_STREAM_DISABLE_ACKED = 0x1,
} DP_VID_STREAM_DISABLE_ACK;
typedef enum DP_VID_STREAM_DISABLE_MASK {
VID_STREAM_DISABLE_MASKED = 0x0,
VID_STREAM_DISABLE_UNMASK = 0x1,
} DP_VID_STREAM_DISABLE_MASK;
typedef enum DPHY_ATEST_SEL_LANE0 {
DPHY_ATEST_LANE0_PRBS_PATTERN = 0x0,
DPHY_ATEST_LANE0_REG_PATTERN = 0x1,
} DPHY_ATEST_SEL_LANE0;
typedef enum DPHY_ATEST_SEL_LANE1 {
DPHY_ATEST_LANE1_PRBS_PATTERN = 0x0,
DPHY_ATEST_LANE1_REG_PATTERN = 0x1,
} DPHY_ATEST_SEL_LANE1;
typedef enum DPHY_ATEST_SEL_LANE2 {
DPHY_ATEST_LANE2_PRBS_PATTERN = 0x0,
DPHY_ATEST_LANE2_REG_PATTERN = 0x1,
} DPHY_ATEST_SEL_LANE2;
typedef enum DPHY_ATEST_SEL_LANE3 {
DPHY_ATEST_LANE3_PRBS_PATTERN = 0x0,
DPHY_ATEST_LANE3_REG_PATTERN = 0x1,
} DPHY_ATEST_SEL_LANE3;
typedef enum DPHY_BYPASS {
DPHY_8B10B_OUTPUT = 0x0,
DPHY_DBG_OUTPUT = 0x1,
} DPHY_BYPASS;
typedef enum DPHY_SKEW_BYPASS {
DPHY_WITH_SKEW = 0x0,
DPHY_NO_SKEW = 0x1,
} DPHY_SKEW_BYPASS;
typedef enum DPHY_TRAINING_PATTERN_SEL {
DPHY_TRAINING_PATTERN_1 = 0x0,
DPHY_TRAINING_PATTERN_2 = 0x1,
DPHY_TRAINING_PATTERN_3 = 0x2,
} DPHY_TRAINING_PATTERN_SEL;
typedef enum DPHY_8B10B_RESET {
DPHY_8B10B_NOT_RESET = 0x0,
DPHY_8B10B_RESETET = 0x1,
} DPHY_8B10B_RESET;
typedef enum DP_DPHY_8B10B_EXT_DISP {
DP_DPHY_8B10B_EXT_DISP_ZERO = 0x0,
DP_DPHY_8B10B_EXT_DISP_ONE = 0x1,
} DP_DPHY_8B10B_EXT_DISP;
typedef enum DPHY_8B10B_CUR_DISP {
DPHY_8B10B_CUR_DISP_ZERO = 0x0,
DPHY_8B10B_CUR_DISP_ONE = 0x1,
} DPHY_8B10B_CUR_DISP;
typedef enum DPHY_PRBS_EN {
DPHY_PRBS_DISABLE = 0x0,
DPHY_PRBS_ENABLE = 0x1,
} DPHY_PRBS_EN;
typedef enum DPHY_PRBS_SEL {
DPHY_PRBS7_SELECTED = 0x0,
DPHY_PRBS23_SELECTED = 0x1,
DPHY_PRBS11_SELECTED = 0x2,
} DPHY_PRBS_SEL;
typedef enum DPHY_LOAD_BS_COUNT_START {
DPHY_LOAD_BS_COUNT_STARTED = 0x0,
DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x1,
} DPHY_LOAD_BS_COUNT_START;
typedef enum DPHY_CRC_EN {
DPHY_CRC_DISABLED = 0x0,
DPHY_CRC_ENABLED = 0x1,
} DPHY_CRC_EN;
typedef enum DPHY_CRC_CONT_EN {
DPHY_CRC_ONE_SHOT = 0x0,
DPHY_CRC_CONTINUOUS = 0x1,
} DPHY_CRC_CONT_EN;
typedef enum DPHY_CRC_FIELD {
DPHY_CRC_START_FROM_TOP_FIELD = 0x0,
DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x1,
} DPHY_CRC_FIELD;
typedef enum DPHY_CRC_SEL {
DPHY_CRC_LANE0_SELECTED = 0x0,
DPHY_CRC_LANE1_SELECTED = 0x1,
DPHY_CRC_LANE2_SELECTED = 0x2,
DPHY_CRC_LANE3_SELECTED = 0x3,
} DPHY_CRC_SEL;
typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x0,
DPHY_FAST_TRAINING_CAPABLE = 0x1,
} DPHY_RX_FAST_TRAINING_CAPABLE;
typedef enum DP_SEC_COLLISION_ACK {
DP_SEC_COLLISION_ACK_NO_EFFECT = 0x0,
DP_SEC_COLLISION_ACK_CLR_FLAG = 0x1,
} DP_SEC_COLLISION_ACK;
typedef enum DP_SEC_AUDIO_MUTE {
DP_SEC_AUDIO_MUTE_HW_CTRL = 0x0,
DP_SEC_AUDIO_MUTE_SW_CTRL = 0x1,
} DP_SEC_AUDIO_MUTE;
typedef enum DP_SEC_TIMESTAMP_MODE {
DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x0,
DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x1,
} DP_SEC_TIMESTAMP_MODE;
typedef enum DP_SEC_ASP_PRIORITY {
DP_SEC_ASP_LOW_PRIORITY = 0x0,
DP_SEC_ASP_HIGH_PRIORITY = 0x1,
} DP_SEC_ASP_PRIORITY;
typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x0,
DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x1,
} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
typedef enum DP_MSE_SAT_UPDATE_ACT {
DP_MSE_SAT_UPDATE_NO_ACTION = 0x0,
DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x1,
DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x2,
} DP_MSE_SAT_UPDATE_ACT;
typedef enum DP_MSE_LINK_LINE {
DP_MSE_LINK_LINE_32_MTP_LONG = 0x0,
DP_MSE_LINK_LINE_64_MTP_LONG = 0x1,
DP_MSE_LINK_LINE_128_MTP_LONG = 0x2,
DP_MSE_LINK_LINE_256_MTP_LONG = 0x3,
} DP_MSE_LINK_LINE;
typedef enum DP_MSE_BLANK_CODE {
DP_MSE_BLANK_CODE_SF_FILLED = 0x0,
DP_MSE_BLANK_CODE_ZERO_FILLED = 0x1,
} DP_MSE_BLANK_CODE;
typedef enum DP_MSE_TIMESTAMP_MODE {
DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x0,
DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x1,
} DP_MSE_TIMESTAMP_MODE;
typedef enum DP_MSE_ZERO_ENCODER {
DP_MSE_NOT_ZERO_FE_ENCODER = 0x0,
DP_MSE_ZERO_FE_ENCODER = 0x1,
} DP_MSE_ZERO_ENCODER;
typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x0,
DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x1,
} DP_MSE_OUTPUT_DPDBG_DATA;
typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
DP_DPHY_HBR2_PASS_THROUGH = 0x0,
DP_DPHY_HBR2_PATTERN_1 = 0x1,
DP_DPHY_HBR2_PATTERN_2_NEG = 0x2,
DP_DPHY_HBR2_PATTERN_3 = 0x3,
DP_DPHY_HBR2_PATTERN_2_POS = 0x6,
} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x0,
DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x1,
} DPHY_CRC_MST_PHASE_ERROR_ACK;
typedef enum DPHY_SW_FAST_TRAINING_START {
DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x0,
DPHY_SW_FAST_TRAINING_STARTED = 0x1,
} DPHY_SW_FAST_TRAINING_START;
typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED= 0x0,
DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x1,
} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x0,
DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x1,
} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x0,
DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x1,
} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
MSA_V_TIMING_OVERRIDE_DISABLED = 0x0,
MSA_V_TIMING_OVERRIDE_ENABLED = 0x1,
} DP_MSA_V_TIMING_OVERRIDE_EN;
typedef enum DP_SEC_GSP0_PRIORITY {
SEC_GSP0_PRIORITY_LOW = 0x0,
SEC_GSP0_PRIORITY_HIGH = 0x1,
} DP_SEC_GSP0_PRIORITY;
typedef enum DP_SEC_GSP0_SEND {
NOT_SENT = 0x0,
FORCE_SENT = 0x1,
} DP_SEC_GSP0_SEND;
typedef enum DP_AUX_CONTROL_HPD_SEL {
DP_AUX_CONTROL_HPD1_SELECTED = 0x0,
DP_AUX_CONTROL_HPD2_SELECTED = 0x1,
DP_AUX_CONTROL_HPD3_SELECTED = 0x2,
DP_AUX_CONTROL_HPD4_SELECTED = 0x3,
DP_AUX_CONTROL_HPD5_SELECTED = 0x4,
DP_AUX_CONTROL_HPD6_SELECTED = 0x5,
} DP_AUX_CONTROL_HPD_SEL;
typedef enum DP_AUX_CONTROL_TEST_MODE {
DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x0,
DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x1,
} DP_AUX_CONTROL_TEST_MODE;
typedef enum DP_AUX_SW_CONTROL_SW_GO {
DP_AUX_SW_CONTROL_SW__NOT_GO = 0x0,
DP_AUX_SW_CONTROL_SW__GO = 0x1,
} DP_AUX_SW_CONTROL_SW_GO;
typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x0,
DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x1,
} DP_AUX_SW_CONTROL_LS_READ_TRIG;
typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x0,
DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x1,
DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x2,
DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x3,
} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x0,
DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x1,
} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x0,
DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x1,
} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
typedef enum DP_AUX_INT_ACK {
DP_AUX_INT__NOT_ACK = 0x0,
DP_AUX_INT__ACK = 0x1,
} DP_AUX_INT_ACK;
typedef enum DP_AUX_LS_UPDATE_ACK {
DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x0,
DP_AUX_INT_LS_UPDATE_ACK = 0x1,
} DP_AUX_LS_UPDATE_ACK;
typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK= 0x0,
DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF= 0x1,
} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x0,
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x1,
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x2,
DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x3,
} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x0,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x1,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x2,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x3,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x4,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x5,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x6,
DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x7,
} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x0,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US= 0x1,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US= 0x3,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US= 0x4,
DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US= 0x5,
} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x0,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x1,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD= 0x3,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD= 0x4,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD= 0x5,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD= 0x6,
DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD= 0x7,
} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD= 0x0,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD= 0x1,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD= 0x3,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD= 0x4,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD= 0x5,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD= 0x6,
DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD= 0x7,
} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES= 0x0,
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES= 0x1,
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2,
DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED= 0x3,
} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x0,
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x1,
} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START= 0x0,
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START= 0x1,
} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP= 0x0,
DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP= 0x1,
} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS= 0x0,
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS= 0x1,
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2,
DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS= 0x3,
} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x0,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x1,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x2,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x3,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x4,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x5,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x6,
DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x7,
} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x0,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x1,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x2,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x3,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x4,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x5,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x6,
DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x7,
} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX= 0x0,
DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX= 0x1,
} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US= 0x0,
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US= 0x1,
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2,
DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US= 0x3,
} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS= 0x0,
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS= 0x1,
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2,
DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED= 0x3,
} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;