)]}'
{
  "commit": "5aa85c9fc49a6ce44dc10a42e2011bbde9dc445a",
  "tree": "14b8d1a014349568be39753f879c152e1e3f2b41",
  "parents": [
    "0f67e90e1caea4a0a14d2c60102547bce29f7f08"
  ],
  "author": {
    "name": "Ralf Baechle",
    "email": "ralf@linux-mips.org",
    "time": "Wed Nov 21 16:39:44 2007 +0000"
  },
  "committer": {
    "name": "Ralf Baechle",
    "email": "ralf@linux-mips.org",
    "time": "Mon Nov 26 17:26:14 2007 +0000"
  },
  "message": "[MIPS] Handle R4000/R4400 mfc0 from count register.\n\nThe R4000 and R4400 have an errata where if the cp0 count register is read\nin the exact moment when it matches the compare register no interrupt will\nbe generated.\n\nThis bug may be triggered if the cp0 count register is being used as\nclocksource and the compare interrupt as clockevent.  So a simple\nworkaround is to avoid using the compare for both facilities on the\naffected CPUs.\n\nThis is different from the workaround suggested in the old errata documents;\nat some opportunity probably the official version should be implemented\nand tested.  Another thing to find out is which processor versions\nexactly are affected.  I only have errata documents upto R4400 V3.0\navailable so for the moment the code treats all R4000 and R4400 as broken.\n\nThis is potencially a problem for some machines that have no other decent\nclocksource available; this workaround will cause them to fall back to\nanother clocksource, worst case the \"jiffies\" source.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "076f52b9bb79225bdfb3b39970d37caba13d8423",
      "old_mode": 33188,
      "old_path": "arch/mips/kernel/cevt-r4k.c",
      "new_id": "24a2d907aa0de4c022c0d5e89227dceae2a8a572",
      "new_mode": 33188,
      "new_path": "arch/mips/kernel/cevt-r4k.c"
    },
    {
      "type": "modify",
      "old_id": "3284b9b4ecac95d6f31bdae2f829f98d5a7eebcb",
      "old_mode": 33188,
      "old_path": "arch/mips/kernel/time.c",
      "new_id": "d7d52efff51f6904a749b1c3e1e689a1ad075c0a",
      "new_mode": 33188,
      "new_path": "arch/mips/kernel/time.c"
    },
    {
      "type": "modify",
      "old_id": "ee1663e64da1aad67162a469c690a605de5e45e7",
      "old_mode": 33188,
      "old_path": "include/asm-mips/time.h",
      "new_id": "1922494a0d9e5f461ab613c5711c26fa0caf4872",
      "new_mode": 33188,
      "new_path": "include/asm-mips/time.h"
    }
  ]
}